Datasheet

ADSP-21371
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications pro-
vided below are valid at the DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
Parameter Min Max Unit
Timing Requirements
t
SISFS
1
FS Setup Before SCLK Rising Edge 3.8 ns
t
SIHFS
1
FS Hold After SCLK Rising Edge 2.5 ns
t
SISD
1
SData Setup Before SCLK Rising Edge 2.5 ns
t
SIHD
1
SData Hold After SCLK Rising Edge 2.5 ns
t
IDPCLKW
Clock Width 9 ns
t
IDPCLK
Clock Period 24 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
DAI_P20 - 1
(SCLK)
DAI_P20
- 1
(FS )
t
SISFS
t
SIHFS
t
IPDCLK
DA I_P 20 - 1
(SDATA)
t
IPDCLKW
t
SISD
t
SIHD
Figure 21. IDP Master Timing
Rev. 0 | Page 33 of 48 | June 2007