Datasheet

ADSP-21371
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-21368 SHARC Processor Hardware
Table 32. Parallel Data Acquisition Port (PDAP)
Reference. Note that the most significant 16 bits of external
PDAP data can be provided through the DATA31–16 pins. The
remaining four bits can only be sourced through DAI_P4–1.
The timing below is valid at the DATA31–16 pins.
Parameter Min Max Unit
Timing Requirements
t
SPCLKEN
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
t
HPCLKEN
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
t
PDSD
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
t
PDHD
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
t
PDCLKW
Clock Width
t
PDCLK
Clock Period
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
t
PDSTRB
PDAP Strobe Pulse Width
2.5
2.5
3.85
2.5
7
24
2 × t
PCLK
+ 3
2 × t
PCLK
– 1
ns
ns
ns
ns
ns
ns
ns
ns
1
Source pins of DATA are DATA31–12 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
DAI_P20 - 1
(PDAP_CLK)
DAI_P20 - 1
(PDAP_CLKEN)
DATA
DAI_P20 - 1
(PDAP_STROBE)
SAMPLE EDGE
t
PDSD
t
PDHD
t
SPCLKEN
t
HPCLKE N
t
PDCLKW
t
PDSTRB
t
PDHLDD
t
PDCLK
Figure 22. PDAP Timing
Rev. 0 | Page 34 of 48 | June 2007