Datasheet

ADSP-21371
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I
2
S, or right justified with word widths of 16-, 18-,
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 24 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
DAI
_
P2
0
-1
LRCLK
DAI_P20-1
SCLK
DAI_P20-1
SDATA
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
LEFT CHANNEL
RIGHT CHANNEL
MSB-1 MSB-2 LSB+2 L SB+1 LSB MSB MSB-1 MSB-2 LSB+2 L SB+1 LSB LSB
MSB
Figure 24. Right-Justified Mode
Figure 25 shows the default I
2
S-justified mode. LRCLK is low
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
DAI_P20-1
LRCLK
DAI_P20-1
SCLK
DAI_P20-1
SDATA
MSB-1 MSB-2 LS B+2 LSB+1 LSB
LEF T CHANNEL
MSB MSB-1 MS B-2 LSB+2 LSB+1 LSB MSB MSB
RIGHT CHANNEL
Figure 25. I
2
S-Justified Mode
Figure 26 shows the left-justified mode. LRCLK is high for the
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
DAI_P20-1
LRCLK
DAI_P20-1
SCLK
DAI_P20-1
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1 MSB-2
LS B+2 LSB +1 LSB
MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB
MSB MSB+1
MSB
Figure 26. Left-Justified Mode
Rev. 0 | Page 36 of 48 | June 2007