Datasheet

ADSP-21371
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 34. Input signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 34. S/PDIF Transmitter Input Data Timing
Parameter Min Max Unit
Timing Requirements
t
SISFS
1
FS Setup Before SCLK Rising Edge 3 ns
t
SIHFS
1
FS Hold After SCLK Rising Edge 3 ns
t
SISD
1
SData Setup Before SCLK Rising Edge 3 ns
t
SIHD
1
SData Hold After SCLK Rising Edge 3 ns
t
SITXCLKW
Transmit Clock Width 9 ns
t
SITXCLK
Transmit Clock Period 20 ns
t
SISCLKW
Clock Width 36 ns
t
SISCLK
Clock Period 80 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
SAMPLE EDGE
t
SISD
t
SISFS
t
SISCLKW
DAI_P20-1
(SDATA)
DAI_P20-1
(TXCLK)
t
SIHD
t
SIHFS
t
SITXCLKW
t
SITXCLK
t
SISCLK
Figure 27. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 35. Over Sampling Clock (TxCLK) Switching Characteristics
Parameter Min Max Unit
TxCLK Frequency for TxCLK = 384 × FS 73.8 MHz
TxCLK Frequency for TxCLK = 256 × FS 49.2 MHz
Frame Rate 192.0 kHz
Rev. 0 | Page 37 of 48 | June 2007