Datasheet

ADSP-21371
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512
× FS clock.
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter Min Max Unit
Switching Characteristics
t
DFSI
LRCLK Delay After SCLK
t
HOFSI
LRCLK Hold After SCLK
t
DDTI
Transmit Data Delay After SCLK
t
HDTI
Transmit Data Hold After SCLK
t
SCLKIW
1
Transmit SCLK Width
–2
–2
38.5
5
5
ns
ns
ns
ns
ns
1
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE EDGE SAMPLE EDGE
t
SCLKIW
t
DFSI
t
DDTI
t
HOFSI
t
HDTI
Figure 28. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. 0 | Page 38 of 48 | June 2007