Datasheet

ADSP-21371
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter Min Max Unit
Timing Requirements
t
SPICLKS
Serial Clock Cycle
t
SPICHS
Serial Clock High Period
t
SPICLS
Serial Clock Low Period
t
SDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
t
HDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
t
SSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
t
SDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active
t
DSDHI
SPIDS Deassertion to Data High Impedance
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
t
HDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
t
DSOV
SPIDS Assertion to Data Out Valid (CPHAS E = 0)
4 × t
PCLK
– 2
2 × t
PCLK
– 2
2 × t
PCLK
– 2
2 × t
PCLK
2 × t
PCLK
2 × t
PCLK
2
2
2 × t
PCLK
0
0
2 × t
PCLK
6.8
6.8
9.5
5 × t
PCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP =
1)
(INPUT)
MISO
MOSI
(INPUT)
(OUTPUT)
CPHASE = 1
MISO
(OUTPUT)
MOSI
(INPUT)
CPHASE = 0
t
HSPIDS
t
DDSPIDS
t
DSDHI
LSB MSB
MSB VALID
t
DSOE
t
DDSPIDS
t
HDSPIDS
t
SSPIDS
t
SDSCO
t
SPICHS
t
SPICLS
t
SPICLS
t
SPICLKS
t
HDS
t
SPICHS
t
SSPIDS
t
HSPIDS
t
DSDHI
LSB VALID
MSB
MSB VALID
t
DDSPIDS
t
SSPIDS
LSB VALID
LSB
t
SDPPW
t
DSOV
t
HDSPIDS
Figure 30. SPI Slave Timing
Rev. 0 | Page 40 of 48 | June 2007