Datasheet

ADSP-21371
TWI Controller Timing
Table 40 and Figure 32 provide timing information for the TWI
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices
1
Parameter
Min
Standard Mode
Max Min
Fast Mode
Max Unit
f
SCL
SCL Clock Frequency 0 100 0 400 kHz
t
HDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated. 4.0 0.6 µs
t
LOW
Low Period of the SCL Clock 4.7 1.3 µs
t
HIGH
High Period of the SCL Clock 4.0 0.6 µs
t
SUSTA
Setup Time for a Repeated Start Condition 4.7 0.6 µs
t
HDDAT
Data Hold Time for TWI-bus Devices 0 0 µs
t
SUDAT
Data Setup Time 250 100 ns
t
SUSTO
Setup Time for Stop Condition 4.0 0.6 µs
t
BUF
Bus Free Time Between a Stop and Start Condition 4.7 1.3 µs
t
SP
Pulse Width of Spikes Suppressed By the Input Filter n/a n/a 0 50 ns
1
All values referred to V
IHmin
and V
ILmax
levels. For more information, see Electrical Characteristics on page 15.
DPI_ P14- 1
SDA
DPI_ P14- 1
SCL
t
LOW
t
HIGH
t
HDSTA
t
HDDAT
t
SUDA T
t
SUSTO
S
t
SUS TA
Sr
t
SP
t
HDS TA
P
S
t
BUF
Figure 32. Fast and Standard Mode Timing on the TWI Bus
Rev. 0 | Page 42 of 48 | June 2007