SHARC Processor ADSP-21477/ADSP-21478/ADSP-21479 SUMMARY The ADSP-2147x processors are available with unique audio-centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more. Factory programmed ROM versions containing latest audio decoders from Dolby and DTS, available to IP licenses For complete ordering information, see Ordering Guide on Page 76.
ADSP-21477/ADSP-21478/ADSP-21479 TABLE OF CONTENTS Summary ............................................................... 1 ESD Sensitivity ................................................... 24 General Description ................................................. 3 Absolute Maximum Ratings ................................... 24 Family Core Architecture ........................................ 4 Timing Specifications ........................................... 25 Family Peripheral Architecture ......
ADSP-21477/ADSP-21478/ADSP-21479 GENERAL DESCRIPTION No Yes No Yes Shift Register IDP/PDAP Yes UART 1 DAI (SRU)/DPI (SRU2) Speed (at 300 MHz) 30.59 μs Speed (at 200 MHz) 45.885 μs 1.66 ns 6.65 ns 2.49 ns 9.975 ns 14.99 ns 26.66 ns 11.61 ns 18.08 ns 22.485 ns 39.99 ns 17.41 ns 27.
ADSP-21477/ADSP-21478/ADSP-21479 The block diagram of the ADSP-2147x on Page 1 also shows the peripheral clock domain (also known as the I/O processor), which contains the following features: elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or register file access. • IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers SIMD mode is supported from external SDRAM but is not supported in the AMI.
ADSP-21477/ADSP-21478/ADSP-21479 buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.
ADSP-21477/ADSP-21478/ADSP-21479 bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchronous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes.
ADSP-21477/ADSP-21478/ADSP-21479 Table 4.
ADSP-21477/ADSP-21478/ADSP-21479 Table 5.
ADSP-21477/ADSP-21478/ADSP-21479 External Memory The external memory interface supports access to the external memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The external ports are comprised of the following modules. • An AMI which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol.
ADSP-21477/ADSP-21478/ADSP-21479 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. Serial ports operate in five modes: • Standard serial mode • Multichannel (TDM) mode External Port Throughput • I2S mode The throughput for the external port, based on 133 MHz clock and 16-bit data bus, is 88 Mbytes/sec for the AMI and 266 Mbytes/sec for SDRAM.
ADSP-21477/ADSP-21478/ADSP-21479 Digital Peripheral Interface (DPI) Pulse-Width Modulation The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two generalpurpose timers.
ADSP-21477/ADSP-21478/ADSP-21479 Shift Register Table 9. DMA Channels (Continued) The shift register can be used as a serial to parallel data converter. The shift register module consists of an 18-stage serial shift register, 18-bit latch, and three-state output buffers. The shift register and latch have separate clocks. Data is shifted into the serial shift register on the positive-going transitions of the shift register serial clock (SR_SCLK) input.
ADSP-21477/ADSP-21478/ADSP-21479 The watch dog timer also has an internal RC oscillator that can be used as the clock source. The internal RC oscillator can be used as an optional alternative to using an external clock applied to the WDT_CLIN pin. Table 10. Boot Mode Selection BOOT_CFG2–01 000 001 010 011 Real-Time Clock The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.
ADSP-21477/ADSP-21478/ADSP-21479 seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page.
ADSP-21477/ADSP-21478/ADSP-21479 ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2147x architecture and functionality. For detailed information on the family core architecture and instruction set, refer to the SHARC Processor Programming Reference.
ADSP-21477/ADSP-21478/ADSP-21479 PIN FUNCTION DESCRIPTIONS Table 11. Pin Descriptions State During/ After Reset Name Type Description ADDR23–0 I/O/T (ipu) High-Z/driven low (boot) External Address. The processor outputs addresses for external memory and peripherals on these pins. The ADDR pins can be multiplexed to support the external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default).
ADSP-21477/ADSP-21478/ADSP-21479 Table 11. Pin Descriptions (Continued) State During/ After Reset Description O/T (ipu) High-Z/ driven high SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDCAS O/T (ipu) High-Z/ driven high SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform.
ADSP-21477/ADSP-21478/ADSP-21479 Table 11. Pin Descriptions (Continued) Name Type THD_P I State During/ After Reset Description Thermal Diode Anode. When not used, this pin can be left floating. THD_M O Thermal Diode Cathode. When not used, this pin can be left floating. MLBCLK I Media Local Bus Clock. This clock is generated by the MLB controller that is synchronized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS = 48 kHz.
ADSP-21477/ADSP-21478/ADSP-21479 Table 11. Pin Descriptions (Continued) Name Type TDI I (ipu) State During/ After Reset Description Test Data Input (JTAG). Provides serial data for the boundary scan logic. High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. TDO O/T TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan.
ADSP-21477/ADSP-21478/ADSP-21479 Table 12. Pin List, Power and Ground 1 Name Type Description VDD_INT P Internal Power Supply. VDD_EXT P I/O Power Supply. VDD_RTC P Real-Time Clock Power Supply. When RTC is not used, this pin should be connected to VDD_EXT. GND1 G Ground. VDD_THD P Thermal Diode Power Supply. When not used, this pin can be left floating. The exposed pad is required to be electrically and thermally connected to GND.
ADSP-21477/ADSP-21478/ADSP-21479 SPECIFICATIONS OPERATING CONDITIONS 200 MHz Parameter VDD_INT VDD_EXT VDD_THD VDD_RTC VIH2 VIL3 VIH_CLKIN3 VIL_CLKIN TJ TJ TJ4 TJ TJ4 TJ4 TJ5 TJ5 1 266 MHz 300 MHz Description Min Nom Max Min Nom Max Min Nom Max Unit Internal (Core) Supply Voltage External (I/O) Supply Voltage Thermal Diode Supply Voltage Real-Time Clock Power Supply Voltage High Level Input Voltage @ VDD_EXT = Max Low Level Input Voltage @ VDD_EXT = Min High Level Input Voltage @ VDD_EXT = Max Lo
ADSP-21477/ADSP-21478/ADSP-21479 ELECTRICAL CHARACTERISTICS 200 MHz 1 Parameter 2 Description Test Conditions Min IDD_INT9 High Level Output Voltage @ VDD_EXT = Min, IOH = –1.0 mA3 Low Level Output Voltage @ VDD_EXT = Min, IOL = 1.
ADSP-21477/ADSP-21478/ADSP-21479 Total Power Dissipation The information in this section should be augmented with Estimating Power for ADSP-214xx SHARC Processors (EE-348). Total power dissipation has two components: Table 13. Activity Scaling Factors (ASF)1 Activity Idle Low Medium Low Medium High Peak-Typical (50:50)2 Peak-Typical (60:40)2 Peak-Typical (70:30)2 High Typical High Peak 1. Internal power consumption is additionally comprised of two components: • Static current due to leakage.
ADSP-21477/ADSP-21478/ADSP-21479 Table 15. Dynamic Current in CCLK Domain—IDD_INT_DYNAMIC (mA, with ASF = 1.0)1, 2 fCCLK (MHz) 100 150 200 266 300 1 2 1.05 V 75 111 N/A N/A N/A 1.10 V 78 117 N/A N/A N/A Voltage (VDD_INT) 1.20 V 1.25 V 86 90 128 134 170 178 225 234 N/A 264 1.15 V 82 122 162 215 N/A 1.35 V 98 146 194 256 291 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 22.
ADSP-21477/ADSP-21478/ADSP-21479 TIMING SPECIFICATIONS fINPUT is the input frequency to the PLL. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times.
ADSP-21477/ADSP-21478/ADSP-21479 PMCTL (SDCKR) PMCTL (PLLBP) CLKIN DIVIDER fINPUT LOOP FILTER VCO fVCO PLL DIVIDER fCCLK CCLK SDRAM DIVIDER BYPASS MUX CLKIN BYPASS MUX PLL XTAL BUF CLK_CFGx/ PMCTL (2 × PLLM) PMCTL (INDIV) PMCTL (PLLD) DIVIDE BY 2 PMCTL (PLLBP) PCLK fVCO ÷ (2 × PLLM) PCLK CCLK RESET DELAY OF 4096 CLKIN CYCLES PIN MUX CLKOUT (TEST ONLY)* RESETOUT Figure 5.
ADSP-21477/ADSP-21478/ADSP-21479 • If the VDD_INT power supply comes up after VDD_EXT, any pin, such as RESETOUT and RESET, may actually drive momentarily until the VDD_INT rail has powered up. Systems sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior. Power-Up Sequencing The timing requirements for processor startup are given in Table 19.
ADSP-21477/ADSP-21478/ADSP-21479 Clock Input Table 20. Clock Input Min Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK2 CCLK Period VCO Frequency fVCO3 tCKJ4, 5 CLKIN Jitter Tolerance 200 MHz Max 40 20 20 5 200 –250 100 45 45 3 10 600 +250 Min 266 MHz Max 301 15 15 3.75 200 –250 100 45 45 3 10 600 +250 1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
ADSP-21477/ADSP-21478/ADSP-21479 mental mode. Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description in Table 11.
ADSP-21477/ADSP-21478/ADSP-21479 Running Reset The following timing specification applies to RESETOUT/ RUNRSTIN pin when it is configured as RUNRSTIN. Table 22. Running Reset Parameter Timing Requirements tWRUNRST Running RESET Pulse Width Low tSRUNRST Running RESET Setup Before CLKIN High Min Max Unit 4 × tCK 8 ns ns CLKIN tWRUNRST tSRUNRST RUNRSTIN Figure 10.
ADSP-21477/ADSP-21478/ADSP-21479 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 24. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min 88-Lead LFCSP Package Max 4 × tPCLK – 1.55 Min All Other Packages Max 4 × tPCLK – 1.2 Unit ns tWCTIM FLAG3 (TMREXP) Figure 12.
ADSP-21477/ADSP-21478/ADSP-21479 Timer WDTH_CAP Timing The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1 pins. Table 26. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width Min Max Unit 2 × tPCLK 2 × (231 – 1) × tPCLK ns Min Max Unit 100 1000 ns 3 7.
ADSP-21477/ADSP-21478/ADSP-21479 Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 28. DAI/DPI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid Min Max Unit 1.5 10 ns DAI_Pn DPI_Pn tDPIO DAI_Pm DPI_Pm Figure 16. DAI Pin to Pin Direct Routing Rev.
ADSP-21477/ADSP-21478/ADSP-21479 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available.
ADSP-21477/ADSP-21478/ADSP-21479 Flags The timing specifications provided below apply to ADDR23–0 and DATA7–0 when configured as FLAGS. See Table 11 on Page 16 for more information on flag use. Table 30. Flags Parameter Timing Requirement FLAGs IN Pulse Width1 tFIPW Switching Characteristic tFOPW FLAGs OUT Pulse Width1 1 Min This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins. FLAG INPUTS tFIPW FLAG OUTPUTS tFOPW Figure 18. Flags Rev.
ADSP-21477/ADSP-21478/ADSP-21479 SDRAM Interface Timing Table 31. SDRAM Interface Timing Parameter Timing Requirements tSSDAT DATA Setup Before SDCLK tHSDAT DATA Hold After SDCLK Switching Characteristics tSDCLK1 SDCLK Period tSDCLKH SDCLK Width High SDCLK Width Low tSDCLKL tDCAD2 Command, ADDR, Data Delay After SDCLK 2 tHCAD Command, ADDR, Data Hold After SDCLK tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK 133 MHz Max Min Min 150 MHz Max Unit 0.7 1.66 0.7 1.5 ns ns 7.5 2.5 2.
ADSP-21477/ADSP-21478/ADSP-21479 AMI Read Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 32. AMI Read Parameter Min Timing Requirements tDAD1, 2, 3 Address Selects Delay to Data Valid tDRLD1, 3 AMI_RD Low to Data Valid tSDS4, 5 Data Setup to AMI_RD High 2.6 tHDRH Data Hold from AMI_RD High 0.
ADSP-21477/ADSP-21478/ADSP-21479 ADDR MSx tDARL tRW tDRHA RD tDRLD tSDS tDAD tHDRH DATA tRWR tDSAK tDAAK ACK WR Figure 20. AMI Read Rev.
ADSP-21477/ADSP-21478/ADSP-21479 AMI Write Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 33.
ADSP-21477/ADSP-21478/ADSP-21479 ADDR MSx tDWHA tDAWH tDAWL tWW WR tWWR tWDE tDATRWH tDDWH tDDWR DATA tDSAK tDWHD tDAAK ACK RD Figure 21. AMI Write Rev.
ADSP-21477/ADSP-21478/ADSP-21479 Serial Ports In slave transmitter mode and master receiver mode, the maximum serial port frequency is fPCLK/8. In master transmitter mode and slave receiver mode, the maximum serial port clock frequency is fPCLK/4. Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
ADSP-21477/ADSP-21478/ADSP-21479 Table 35.
ADSP-21477/ADSP-21478/ADSP-21479 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) DAI_P20–1 (SCLK) tDFSIR tDFSE tSFSI tHOFSIR tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK
ADSP-21477/ADSP-21478/ADSP-21479 Table 36. Serial Ports—External Late Frame Sync 88-Lead LFCSP Package All Other Packages Min Max Min Max Parameter Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 1 2 × tPCLK 0.5 13.5 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.
ADSP-21477/ADSP-21478/ADSP-21479 Table 37. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK tDDTTE1 Data Disable from External Transmit SCLK 1 tDDTIN Data Enable from Internal Transmit SCLK 1 88-Lead LFCSP Package Min Max Min 2 2 All Other Packages Max 23 –1 20 –1 Referenced to drive edge.
ADSP-21477/ADSP-21478/ADSP-21479 The SPORTx_TDV_O output signal (routing unit) becomes active in SPORT multichannel/packed mode. During transmit slots (enabled with active channel selection registers), the SPORTx_TDV_O is asserted for communication with external devices. Table 38.
ADSP-21477/ADSP-21478/ADSP-21479 Input Data Port (IDP) The timing requirements for the IDP are given in Table 39. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 39.
ADSP-21477/ADSP-21478/ADSP-21479 PDAP chapter of the ADSP-214xx SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the ADDR23–0 pins or over the DAI pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 40. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the Table 40.
ADSP-21477/ADSP-21478/ADSP-21479 Sample Rate Converter—Serial Input Port The ASRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 41 are valid at the DAI_P20–1 pins. Table 41.
ADSP-21477/ADSP-21478/ADSP-21479 delay specification with regard to serial clock. Note that serial clock rising edge is the sampling edge and the falling edge is the drive edge. Sample Rate Converter—Serial Output Port For the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and Table 42.
ADSP-21477/ADSP-21478/ADSP-21479 Pulse-Width Modulation Generators (PWM) The following timing specifications apply when the ADDR23–8/DPI_14–1 pins are configured as PWM. Table 43. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period 88-Lead LFCSP Package Max Min tPCLK – 2 2 × tPCLK – 2 (216 – 2) × tPCLK (216 – 1) × tPCLK tPWMW PWM OUTPUTS tPWMP Figure 30. PWM Timing Rev.
ADSP-21477/ADSP-21478/ADSP-21479 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is rightjustified to the next frame sync transition.
ADSP-21477/ADSP-21478/ADSP-21479 Table 46. S/PDIF Transmitter Left-Justified Mode Parameter Timing Requirement tLJD FS to MSB Delay in Left-Justified Mode DAI_P20–1 FS LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 33. Left-Justified Mode Rev.
ADSP-21477/ADSP-21478/ADSP-21479 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 47. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 47.
ADSP-21477/ADSP-21478/ADSP-21479 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 49.
ADSP-21477/ADSP-21478/ADSP-21479 SPI Interface—Master Both the primary and secondary SPIs are available through DPI only. The timing provided in Table 50 and Table 51 applies to both. Table 50.
ADSP-21477/ADSP-21478/ADSP-21479 SPI Interface—Slave Table 51.
ADSP-21477/ADSP-21478/ADSP-21479 Media Local Bus All the numbers given are applicable for all speed modes (1024 FS, 512 FS, and 256 FS for 3-pin; 512 FS and 256 FS for 5-pin) unless otherwise specified. Please refer to MediaLB specification document rev 3.0 for more details. Table 52.
ADSP-21477/ADSP-21478/ADSP-21479 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLBCLK tMCKR tMCKL tMCKF tMLBCLK tMCFDZ tMCDRV tMDZH MLBSIG/ MLBDAT (Tx, Output) VALID Figure 38. MLB Timing (3-Pin Interface) Table 53.
ADSP-21477/ADSP-21478/ADSP-21479 MLBSIG/ MLBDAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLBCLK tMCKR tMCKL tMCKF tMLBCLK tMCRDL tMCDRV VALID MLBSO/ MLBDO (Tx, Output) Figure 39. MLB Timing (5-Pin Interface) MLBCLK tMPWV tMPWV Figure 40. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Rev.
ADSP-21477/ADSP-21478/ADSP-21479 Shift Register Table 54.
ADSP-21477/ADSP-21478/ADSP-21479 tSSDI,tSSDIDAI DAI_P08-01 OR SR_SCLK tHSDI,tHSDIDAI DAI_P08-01 OR SR_SDI SR_SDO Figure 41. SR_SDI Setup, Hold SR_SCLK OR DAI_P08-01 OR DAI_P20-01(SPx_CLK_O) OR DAI_P20-01(PCG_CLKx_O) tDSDO2 tDSDO1 SR_SDO THE TIMING PARAMETERS SHOWN FOR tDSDO1 AND tDSDO2 ARE VALID FOR tDSDODAI1, tDSDOSP1, tDSDOPCG1, tDSDODAI2, tDSDOSP2, AND tDSDOPCG2 Figure 42.
ADSP-21477/ADSP-21478/ADSP-21479 SR_SCLK OR DAI_P08-01 tSSCK2LCK tSSCK2LCKDAI SR_LAT OR DAI_P08-01 SR_SDI OR DAI_P08-01 SR_LDO Figure 44. SR_SCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency tCLRW SR_CLR tCLRREM2SCK SR_SDCLK OR DAI_P08-01 tCLRREM2LCK SR_LAT OR DAI_P08-01 tDSDOCLR2 tDSDOCLR1 SR_SDO tDLDOCLR2 tDLDOCLR1 SR_LDO Figure 45. Shift Register Reset Timing Rev.
ADSP-21477/ADSP-21478/ADSP-21479 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. 2-Wire Interface (TWI)—Receive and Transmit Timing For information on the TWI receive and transmit operations, see the ADSP-214xx SHARC Hardware Reference Manual. JTAG Test Access Port and Emulation Table 55.
ADSP-21477/ADSP-21478/ADSP-21479 OUTPUT DRIVE CURRENTS TESTER PIN ELECTRONICS Table 56 shows the driver types and the pins associated with each driver. Figure 47 shows typical I-V characteristics for each driver. The curves represent the current drive capability of the output drivers as a function of output voltage. 50: VLOAD T1 70: Table 56.
ADSP-21477/ADSP-21478/ADSP-21479 where: 14 TJ = junction temperature (°C) TYPE A DRIVE FALL y = 0.0748x + 0.4601 RISE AND FALL TIMES (ns) 12 TCASE = case temperature (°C) measured at the top center of the package TYPE A DRIVE RISE y = 0.0567x + 0.482 10 TYPE B DRIVE FALL y = 0.0367x + 0.4502 8 PD = power dissipation Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first order approximation of TJ by the equation: 6 TYPE B DRIVE RISE y = 0.
ADSP-21477/ADSP-21478/ADSP-21479 Thermal Diode where: The processors incorporate thermal diode/s to monitor the die temperature. The thermal diode is a grounded collector, PNP bipolar junction transistor (BJT). The THD_P pin is connected to the emitter, and the THD_M pin is connected to the base of the transistor. These pins can be used by an external temperature sensor (such as ADM1021A or LM86 or others) to read the die temperature of the chip.
ADSP-21477/ADSP-21478/ADSP-21479 88-LFCSP_VQ LEAD ASSIGNMENT Table 61 lists the 88-Lead LFCSP_VQ package lead names. Table 61. 88-Lead LFCSP_VQ Lead Assignments (Numerical by Lead Number) Lead Name CLK_CFG1 BOOT_CFG0 VDD_EXT VDD_INT BOOT_CFG1 GND CLK_CFG0 VDD_INT CLKIN XTAL VDD_EXT VDD_INT VDD_INT RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No.
ADSP-21477/ADSP-21478/ADSP-21479 Figure 53 shows the top view of the 88-lead LFCSP_VQ pin configuration. Figure 54 shows the bottom view. PIN 88 PIN 67 PIN 1 PIN 66 PIN 1 INDICATOR ADSP-2147x 88-LEAD LFCSP_VQ TOP VIEW PIN 22 PIN 45 PIN 23 PIN 44 Figure 53. 88-Lead LFCSP_VQ Lead Configuration (Top View) PIN 67 PIN 88 PIN 66 PIN 1 ADSP-2147x 88-LEAD LFCSP_VQ BOTTOM VIEW GND PAD (PIN 89) PIN 1 INDICATOR PIN 45 PIN 22 PIN 44 PIN 23 Figure 54.
ADSP-21477/ADSP-21478/ADSP-21479 100-LQFP_EP LEAD ASSIGNMENT Table 62 lists the 100-Lead LQFP_EP lead names. Table 62. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number) Lead Name VDD_INT CLK_CFG1 BOOT_CFG0 VDD_EXT VDD_INT BOOT_CFG1 GND NC NC CLK_CFG0 VDD_INT CLKIN XTAL VDD_EXT VDD_INT VDD_INT RESETOUT/RUNRSTIN VDD_INT DPI_P01 DPI_P02 DPI_P03 VDD_INT DPI_P05 DPI_P04 DPI_P06 Lead No.
ADSP-21477/ADSP-21478/ADSP-21479 Figure 55 shows the top view configuration of the 100-lead LQFP_EP package. Figure 56 shows the bottom view configuration of the 100-lead LQFP_EP package. LEAD 100 LEAD 76 LEAD 1 LEAD 75 LEAD 1 INDICATOR ADSP-2147x 100-LEAD LQFP_EP TOP VIEW LEAD 25 LEAD 51 LEAD 26 LEAD 50 Figure 55.
ADSP-21477/ADSP-21478/ADSP-21479 196-BGA BALL ASSIGNMENT Table 63. 196-Ball CSP_BGA Ball Assignment (Numerical by Ball No.) Ball No.
ADSP-21477/ADSP-21478/ADSP-21479 OUTLINE DIMENSIONS The processors are available in 88-lead LFCSP_VQ, 100-lead LQFP_EP and 196-ball CSP_BGA RoHS compliant packages. For package assignment by model, see Ordering Guide on Page 76. 12.10 12.00 SQ 11.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 88 67 66 1 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 11.85 11.75 SQ 11.65 0.50 0.40 0.30 SEATING PLANE 12° MAX 22 45 44 23 BOTTOM VIEW TOP VIEW *0.90 0.85 0.75 0.70 0.65 0.60 10.
ADSP-21477/ADSP-21478/ADSP-21479 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 14.20 14.00 SQ 13.80 100 12.00 REF 76 1 1.00 REF 76 75 100 1 75 PIN 1 SEATING PLANE EXPOSED PAD TOP VIEW 1.45 1.40 1.35 0.20 0.09 0.15 0.05 7° 0° 26 51 (PINS UP) 51 50 25 26 50 0.27 0.22 0.17 VIEW A 0.08 COPLANARITY BOTTOM VIEW (PINS DOWN) 25 0.50 BSC LEAD PITCH FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
ADSP-21477/ADSP-21478/ADSP-21479 SURFACE-MOUNT DESIGN AUTOMOTIVE PRODUCTS For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. The ADSP-21477, ADSP-21478, and ADSP-21479 are available with controlled manufacturing to support the quality and reliability requirements of automotive applications.
ADSP-21477/ADSP-21478/ADSP-21479 ORDERING GUIDE Model1 ADSP-21477KCPZ-1A ADSP-21477KSWZ-1A ADSP-21477BCPZ-1A ADSP-21478KCPZ-1A ADSP-21478BCPZ-1A ADSP-21478BBCZ-2A ADSP-21478BSWZ-2A ADSP-21478KBCZ-1A ADSP-21478KBCZ-2A ADSP-21478KBCZ-3A ADSP-21478KSWZ-1A ADSP-21478KSWZ-2A ADSP-21479KCPZ-1A ADSP-21479BCPZ-1A ADSP-21479BBCZ-2A ADSP-21479BSWZ-2A ADSP-21479KBCZ-1A ADSP-21479KBCZ-2A ADSP-21479KBCZ-3A ADSP-21479KSWZ-1A ADSP-21479KSWZ-2A Temperature Range2 0°C to +70°C 0°C to +70°C –40C to +85C 0°C to +70°C –40
