Datasheet

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B | Page 23 of 68 | March 2013
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 18. All
of the timing specifications for the ADSP-2148x peripherals are
defined in relation to t
PCLK
. See the peripheral specific section
for each peripheral’s timing information.
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 19. While no specific power-up sequencing is required
between V
DD_EXT
and V
DD_INT
, there are some considerations
that system designs should take into account.
• No power supply should be powered up for an extended
period of time (> 200 ms) before another supply starts to
ramp up.
•If the V
DD_INT
power supply comes up after V
DD_EXT
, any
pin, such as RESETOUT
and RESET, may actually drive
momentarily until the V
DD_INT
rail has powered up.
Systems sharing these signals on the board must determine
if there are any issues that need to be addressed based on
this behavior.
Note that during power-up, when the V
DD_INT
power supply
comes up after V
DD_EXT
, a leakage current of the order of three-
state leakage current pull-up, pull-down may be observed on
any pin, even if that is an input only (for example the RESET
pin) until the V
DD_INT
rail has powered up.
Table 18. Clock Periods
Timing
Requirements Description
t
CK
CLKIN Clock Period
t
CCLK
Processor Core Clock Period
t
PCLK
Peripheral Clock Period = 2 × t
CCLK
t
SDCLK
SDRAM Clock Period = (t
CCLK
) × SDCKR
Table 19. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DD_EXT
or V
DD_INT
On 0 ms
t
IVDDEVDD
V
DD_INT
On Before V
DD_EXT
–200 +200 ms
t
CLKVDD
1
CLKIN Valid After V
DD_INT
and V
DD_EXT
Valid 0 200 ms
t
CLKRST
CLKIN Valid Before RESET Deasserted 10
2
µs
t
PLLRST
PLL Control Setup Before RESET Deasserted 20
3
µs
Switching Characteristic
t
CORERST
4, 5
Core Reset Deasserted After RESET Deasserted 4096 × t
CK
+ 2 × t
CCLK
1
Valid V
DD_INT
and V
DD_EXT
assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary
from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in Table 21. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.