Datasheet

Rev. B | Page 24 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Clock Input
Figure 5. Power-Up Sequencing
Table 20. Clock Input
Parameter
300 MHz 350 MHz 400 MHz 450 MHz
UnitMin Max Min Max Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 26.66
1
1
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
100
2
2
Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
22.8
1
100
2
20
1
100
2
17.75
1
100
2
ns
t
CKL
CLKIN Width Low 13 45 11 45 10 45 8.875 45 ns
t
CKH
CLKIN Width High 13 45 11 45 10 45 8.875 45 ns
t
CKRF
3
3
Guaranteed by simulation but not tested on silicon.
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 ns
t
CCLK
4
4
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CCLK Period 3.33 10 2.85 10 2.5 10 2.22 10 ns
f
VCO
5
5
See Figure 4 on Page 22 for VCO diagram.
VCO Frequency 200 800 200 800 200 800 200 900 MHz
t
CKJ
6, 7
6
Actual input jitter should be combined with ac specifications for accurate timing analysis.
7
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 ps
Figure 6. Clock Input
t
RSTVDD
t
CLKVDD
t
CLKRST
t
CORERST
t
PLLRST
V
DDEXT
V
DDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
t
IVDDEVDD
CLKIN
t
CK
t
CKL
t
CKH
t
CKJ