Datasheet

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B | Page 25 of 68 | March 2013
Clock Signals
The ADSP-2148x can use an external clock or a crystal. See the
CLKIN pin description in Table 11 on Page 14. Programs can
configure the processor to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 7 shows the component connections used for a crystal
operating in fundamental mode. Note that the clock rate is
achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Figure 7. Recommended Circuit for
Fundamental Mode Crystal Operation
C
1
2
2pF
Y1
R1
0ȍ
XTAL
CLKIN
C2
22pF
25MHz
R2
47ȍ
TYPICAL VALUES
ADSP-2148x
CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE
POWER. REFER TO CRYSTAL MANUFACTURER’S
SPECIFICATIONS.