Datasheet

Rev. B | Page 32 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SDRAM Interface Timing (166 MHz SDCLK)
The maximum frequency for SDRAM is 166 MHz. For informa-
tion on SDRAM frequency and programming, see the
ADSP-214xx SHARC Processor Hardware Reference, Engineer-
to-Engineer Note “Interfacing SDRAM Memories to SHARC
Processors” (EE-286), and the SDRAM vendor data sheet.
Table 31. SDRAM Interface Timing
Parameter Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before SDCLK 0.7 ns
t
HSDAT
DATA Hold After SDCLK 1.23 ns
Switching Characteristics
t
SDCLK
1
SDCLK Period 6 ns
t
SDCLKH
SDCLK Width High 2.2 ns
t
SDCLKL
SDCLK Width Low 2.2 ns
t
DCAD
2
Command, ADDR, Data Delay After SDCLK 4 ns
t
HCAD
2
Command, ADDR, Data Hold After SDCLK 1 ns
t
DSDAT
Data Disable After SDCLK 5.3 ns
t
ENSDAT
Data Enable After SDCLK 0.3 ns
1
Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 166 MHz the
SDRAM model with a speed grade of 183 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM Memories to SHARC Processors” (EE-286) for
more information on hardware design guidelines for the SDRAM interface.
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
Figure 18. SDRAM Interface Timing
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
t
SDCLKH
t
SDCLKL
t
HSDAT
t
SSDAT
t
HCAD
t
DCAD
t
ENSDAT
t
DCAD
t
DSDAT
t
HCAD
t
SDCLK