Datasheet

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B | Page 35 of 68 | March 2013
AMI Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD
,
AMI_WR
, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 33. AMI Write
Parameter Min Max Unit
Timing Requirements
t
DAAK
1, 2
AMI_ACK Delay from Address, Selects t
SDCLK
– 9.7 + W ns
t
DSAK
1, 3
AMI_ACK Delay from AMI_WR Low W – 6 ns
Switching Characteristics
t
DAWH
2
Address Selects to AMI_WR Deasserted t
SDCLK
–3.1+ W ns
t
DAWL
2
Address Selects to AMI_WR Low t
SDCLK
–3 ns
t
WW
AMI_WR Pulse Width W – 1.3 ns
t
DDWH
Data Setup Before AMI_WR High t
SDCLK
–3.7+ W ns
t
DWHA
Address Hold After AMI_WR Deasserted H + 0.15 ns
t
DWHD
Data Hold After AMI_WR Deasserted H ns
t
DATRWH
4
Data Disable After AMI_WR Deasserted t
SDCLK
– 4.3 + H t
SDCLK
+ 4.9 + H ns
t
WWR
5
AMI_WR High to AMI_WR Low t
SDCLK
–1.5+ H ns
t
DDWR
Data Disable Before AMI_RD Low 2 × t
SDCLK
– 6 ns
t
WDE
AMI_WR Low to Data Enabled t
SDCLK
– 3.7 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
1
AMI_ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of AMI_ACK (low).
2
The falling edge of MSx is referenced.
3
Note that timing for AMI_ACK, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 55 for calculation of hold times given capacitive and dc loads.
5
For Write to Write: t
SDCLK
+ H, for both same bank and different bank. For Write to Read: 3 × t
SDCLK
+ H, for the same bank and different banks.
Figure 20. AMI Write
AMI_ACK
AMI_DATA
t
DAWH
t
DWHA
t
WWR
t
DATRWH
t
DWHD
t
WW
t
DDWR
t
DDWH
t
DAWL
t
WDE
t
DSAK
t
DAAK
AMI_RD
AMI_WR
AMI_ADDR
AMI_MSx