Datasheet

Rev. B | Page 36 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Serial Ports
In slave transmitter mode and master receiver mode, the maxi-
mum serial port frequency is f
PCLK
/8. In master transmitter
mode and slave receiver mode, the maximum serial port clock
frequency is f
PCLK
/4. To determine whether communication is
possible between two devices at clock speed n, the following
specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold; 2) data delay and data setup and hold; and
3) SCLK width.
Serial port signals (SCLK, frame sync, Data Channel A, Data
Channel B) are routed to the DAI_P20–1 pins using the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Table 34. Serial Ports—External Clock
Parameter Min Max Unit
Timing Requirements
t
SFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive
Mode)
2.5
ns
t
HFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive
Mode)
2.5
ns
t
SDRE
1
Receive Data Setup Before Receive SCLK 1.9 ns
t
HDRE
1
Receive Data Hold After SCLK 2.5 ns
t
SCLKW
SCLK Width (t
PCLK
× 4) ÷ 2 – 1.5 ns
t
SCLK
SCLK Period t
PCLK
× 4 ns
Switching Characteristics
t
DFSE
2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
10.25
ns
t
HOFSE
2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
2
ns
t
DDTE
2
Transmit Data Delay After Transmit SCLK 9 ns
t
HDTE
2
Transmit Data Hold After Transmit SCLK 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 35. Serial Ports—Internal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
7
ns
t
HFSI
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
2.5
ns
t
SDRI
1
Receive Data Setup Before SCLK 7 ns
t
HDRI
1
Receive Data Hold After SCLK 2.5 ns
Switching Characteristics
t
DFSI
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 4 ns
t
HOFSI
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1 ns
t
DFSIR
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 9.75 ns
t
HOFSIR
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1 ns
t
DDTI
2
Transmit Data Delay After SCLK 3.25 ns
t
HDTI
2
Transmit Data Hold After SCLK –2 ns
t
SCKLIW
Transmit or Receive SCLK Width 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.