Datasheet

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B | Page 45 of 68 | March 2013
Pulse-Width Modulation Generators (PWM)
The following timing specifications apply when the
ADDR23–8/DPI_14–1 pins are configured as PWM.
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left-justified, I
2
S, or right-justified with word widths of 16, 18,
20, or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 30 shows the right-justified mode. Frame sync is high for
the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum
in 24-bit output mode or the maximum in 16-bit output mode
from a frame sync transition, so that when there are 64 serial
clock periods per frame sync period, the LSB of the data is right-
justified to the next frame sync transition.
Table 43. Pulse-Width Modulation (PWM) Timing
Parameter Min Max Unit
Switching Characteristics
t
PWMW
PWM Output Pulse Width t
PCLK
– 2 (2
16
– 2) × t
PCLK
ns
t
PWMP
PWM Output Period 2 × t
PCLK
– 1.5 (2
16
– 1) × t
PCLK
ns
Figure 29. PWM Timing
PWM
OUTPUTS
t
PWMW
t
PWMP
Table 44. S/PDIF Transmitter Right-Justified Mode
Parameter Nominal Unit
Timing Requirement
t
RJD
Frame Sync to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
16
14
12
8
SCLK
SCLK
SCLK
SCLK
Figure 30. Right-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
RJD