Datasheet

Rev. B | Page 48 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter Min Max Unit
Switching Characteristics
t
DFSI
Frame Sync Delay After Serial Clock 5 ns
t
HOFSI
Frame Sync Hold After Serial Clock –2 ns
t
DDTI
Transmit Data Delay After Serial Clock 5 ns
t
HDTI
Transmit Data Hold After Serial Clock –2 ns
t
SCLKIW
1
Transmit Serial Clock Width 8 × t
PCLK
– 2 ns
1
SCLK frequency is 64 × FS where FS = the frequency of frame sync.
Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE EDGE
t
SCLKIW
t
DFSI
t
HOFSI
t
DDTI
t
HDTI