Datasheet

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B | Page 51 of 68 | March 2013
Media Local Bus
All the numbers given are applicable for all speed modes
(1024 FS, 512 FS and 256 FS for 3-pin; 512 FS and 256 FS for
5-pin), unless otherwise specified. Please refer to the MediaLB
specification document revision 3.0 for more details.
Table 52. MLB Interface, 3-Pin Specifications
Parameter Min Typ Max Unit
3-Pin Characteristics
t
MLBCLK
MLB Clock Period
1024 FS
512 FS
256 FS
20.3
40
81
ns
ns
ns
t
MCKL
MLBCLK Low Time
1024 FS
512 FS
256 FS
6.1
14
30
ns
ns
ns
t
MCKH
MLBCLK High Time
1024 FS
512 FS
256 FS
9.3
14
30
ns
ns
ns
t
MCKR
MLBCLK Rise Time (V
IL
to V
IH
)
1024 FS
512 FS/256 FS
1
3
ns
ns
t
MCKF
MLBCLK Fall Time (V
IH
to V
IL
)
1024 FS
512 FS/256 FS
1
3
ns
ns
t
MPWV
1
MLBCLK Pulse Width Variation
1024 FS
512 FS/256
0.7
2.0
nspp
nspp
t
DSMCF
DAT/SIG Input Setup Time 1 ns
t
DHMCF
DAT/SIG Input Hold Time 2 ns
t
MCFDZ
DAT/SIG Output Time to Three-state 0 15 ns
t
MCDRV
DAT/SIG Output Data Delay From MLBCLK Rising Edge 8 ns
t
MDZH
2
Bus Hold Time
1024 FS
512 FS/256
2
4
ns
ns
C
MLB
DAT/SIG Pin Load
1024 FS
512 FS/256
40
60
pf
pf
1
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
2
The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be
minimized while meeting the maximum capacitive load listed.