Datasheet

Rev. B | Page 52 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 37. MLB Timing (3-Pin Interface)
Table 53. MLB Interface, 5-Pin Specifications
Parameter Min Typ Max Unit
5-Pin Characteristics
t
MLBCLK
MLB Clock Period
512 FS
256 FS
40
81
ns
ns
t
MCKL
MLBCLK Low Time
512 FS
256 FS
15
30
ns
ns
t
MCKH
MLBCLK High Time
512 FS
256 FS
15
30
ns
ns
t
MCKR
MLBCLK Rise Time (V
IL
to V
IH
)6ns
t
MCKF
MLBCLK Fall Time (V
IH
to V
IL
)6ns
t
MPWV
1
MLBCLK Pulse Width Variation 2 nspp
t
DSMCF
2
DAT/SIG Input Setup Time 3 ns
t
DHMCF
DAT/SIG Input Hold Time 5 ns
t
MCDRV
DS/DO Output Data Delay From MLBCLK Rising Edge 8 ns
t
MCRDL
3
DO/SO Low From MLBCLK High
512 FS
256 FS
10
20
ns
ns
C
MLB
DS/DO Pin Load 40 pf
1
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
2
Gate Delays due to OR'ing logic on the pins must be accounted for.
3
When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,
external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.
t
MCKH
MLBSIG/
MLBDAT
(Rx, Input)
t
MCKL
t
MCKR
MLBSIG/
MLBDAT
(Tx, Output)
t
MCFDZ
t
DSMCF
MLBCLK
t
MLBCLK
VALID
t
DHMCF
t
MCKF
t
MCDRV
VALID
t
MDZH