Datasheet

Rev. B | Page 54 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
JTAG Test Access Port and Emulation
Table 54. JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 ns
t
STAP
TDI, TMS Setup Before TCK High 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
1
1
System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0.
System Inputs Setup Before TCK High 7 ns
t
HSYS
1
System Inputs Hold After TCK High 18 ns
t
TRSTW
TRST Pulse Width 4t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 ns
t
DSYS
2
2
System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU.
System Outputs Delay After TCK Low t
TCK
÷ 2 + 7 ns
Figure 40. IEEE 1149.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS