DSP Microcomputers Instructions Manual

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FUNCTIONAL BLOCK DIAGRAM

DSP Microcomputers

ADSP-2181/ADSP-2183

FEATURES

PERFORMANCE

30 ns Instruction Cycle Time @ 5.0 Volts

33 MIPS Sustained Performance

34.7 ns Instruction Cycle Time @ 3.3 Volts

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 100 Cycle Recovery from

Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Memory RAM

16K Words On-Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator, & Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides

Zero Overhead Looping

Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

128-Lead TQFP/128-Lead PQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory

4 MByte Memory Interface for Storage of Data Tables &

Program Overlays

8-Bit DMA to Byte Memory for Transparent

Program and Data Memory Transfers

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals

Programmable Memory Strobe & Separate I/O Memory

Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

ICE-Port™ Emulator Interface Supports Debugging

in Final Systems

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

ICE-Port is a trademark of Analog Devices, Inc.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

GENERAL DESCRIPTION

The ADSP-2181/ADSP-2183 is a single-chip microcomputer

optimized for digital signal processing (DSP) and other high

speed numeric processing applications.

The ADSP-2181/ADSP-2183 combines the ADSP-2100 family

base architecture (three computational units, data address gen-

erators and a program sequencer) with two serial ports, a 16-bit

internal DMA port, a byte DMA port, a programmable timer,

Flag I/O, extensive interrupt capabilities, and on-chip program

and data memory.

The ADSP-2181/ADSP-2183 integrates 80K bytes of on-chip

memory configured as 16K words (24-bit) of program RAM,

and 16K words (16-bit) of data RAM. Power down circuitry is

also provided to meet the low power needs of battery operated

portable equipment. The ADSP-2181 is available in 128-pin

TQFP and 128-pin PQFP packages; the ADSP-2183 is avail-

able in the TQFP package only.

In addition, the ADSP-2181/ADSP-2183 supports new instruc-

tions, which include bit manipulations—bit set, bit clear, bit toggle,

bit test—new ALU constants, new multiplication instruction

(x squared), biased rounding, result free ALU operations, I/O memory

transfers, and global interrupt masking, for increased flexibility.

Fabricated in a high speed, double metal, low power, 0.5 µm

CMOS process, the ADSP-2181 operates with a 30 ns instruc-

tion cycle time (34.7 ns for the ADSP-2183). Every instruction

can execute in a single processor cycle.

The ADSP-2181/ADSP-2183’s flexible architecture and com-

prehensive instruction set allow the processor to perform multiple

operations in parallel. In one processor cycle the ADSP-2181/

ADSP-2183 can:

• generate the next program address

• fetch the next instruction

• perform one or two data moves

• update one or two data address pointers

• perform a computational operation

SERIAL PORTS

MEMORY

FLAGS

PROGRAMMABLE

I/O

BYTE DMA

CONTROLLER

PROGRAM

MEMORY

DATA

MEMORY

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

DMA

BUS

INTERNAL

DMA

PORT

TIMER

SPORT 1SPORT 0

ADSP-2100 BASE

ARCHITECTURE

SHIFTER

MAC

ALU

ARITHMETIC UNITS

POWERDOWN

CONTROL

PROGRAM

SEQUENCER

DAG 0

DAG 1

DATA ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

Summary of content (40 pages)

PAGE 1
a FEATURES PERFORMANCE 30 ns Instruction Cycle Time @ 5.0 Volts 33 MIPS Sustained Performance 34.7 ns Instruction Cycle Time @ 3.
PAGE 2
ADSP-2181/ADSP-2183 This takes place while the processor continues to: • receive and transmit data through the two serial ports • receive and/or transmit data through the internal DMA port • receive and/or transmit data through the byte DMA port • decrement timer Additional Information This data sheet provides a general overview of ADSP-2181/ ADSP-2183 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User’s Manual.
PAGE 3
ADSP-2181/ADSP-2183 Program memory can store both instructions and data, permitting the ADSP-2181/ADSP-2183 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2181/ADSP-2183 can fetch an operand from program memory and the next instruction in the same cycle. In addition to the address and data bus for external memory connection, the ADSP-2181/ADSP-2183 has a 16-bit Internal DMA port (IDMA port) for connection to external systems.
PAGE 4
ADSP-2181/ADSP-2183 • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711. Pin Name(s) • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. # of Pins CLKOUT 1 SPORT0 5 SPORT1 5 Input/ Output Function • SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream.
PAGE 5
ADSP-2181/ADSP-2183 Table I.
PAGE 6
ADSP-2181/ADSP-2183 When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2181/ADSP-2183 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation.
PAGE 7
ADSP-2181/ADSP-2183 Table II. Memory Architecture The ADSP-2181/ADSP-2183 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2181/ADSP-2183 has 16K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using the external data bus.
PAGE 8
ADSP-2181/ADSP-2183 There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal.
PAGE 9
ADSP-2181/ADSP-2183 When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. Table VI.
PAGE 10
ADSP-2181/ADSP-2183 If the ADSP-2181/ADSP-2183 is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses.
PAGE 11
ADSP-2181/ADSP-2183 These ADSP-2181/ADSP-2183 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2181/ADSP-2183 and the connector must be kept as short as possible, no longer that 3 inches.
PAGE 12
ADSP-2181–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter VDD TAMB Supply Voltage Ambient Operating Temperature B Grade Min Max Min Max Unit 4.5 0 5.5 +70 4.5 –40 5.
PAGE 13
ADSP-2181/ADSP-2183 ADSP-2181 ABSOLUTE MAXIMUM RATINGS * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . .
PAGE 14
ADSP-2181/ADSP-2183 (C × VDD2 × f ) is calculated for each output: ADSP-2181 # of Pins × C ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: TAMB = TCASE – (PD × θ CA) TCASE = Case Temperature in °C PD = Power Dissipation in W θ CA = Thermal Resistance (Case-to-Ambient) θ JA = Thermal Resistance (Junction-to-Ambient) θ JC = Thermal Resistance (Junction-to-Case) Address, DMS Data Output, WR RD CLKOUT ×f ×5 V × 52 V × 52 V × 52 V × 33.3 MHz × 16.67 MHz × 16.67 MHz × 33.3 MHz 2 = 66.6 mW = 37.
PAGE 15
ADSP-2181/ADSP-2183 ADSP-2181 tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: CAPACITIVE LOADING Figures 10 and 11 show the capacitive loading characteristics of the ADSP-2181. t DECAY = from which 30 T = +85°C VDD = 4.5V t DIS = t MEASURED – t DECAY 25 RISE TIME (0.4V–2.4V) – ns CL • 0.5V iL is calculated.
PAGE 16
ADSP-2181/ADSP-2183 ADSP-2183–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter VDD TAMB Supply Voltage Ambient Operating Temperature B Grade Min Max Min Max Unit 3.0 0 3.6 +70 3.0 –40 3.
PAGE 17
ADSP-2181/ADSP-2183 ADSP-2183 ABSOLUTE MAXIMUM RATINGS * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Operating Temperature Range (Ambient) . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . .
PAGE 18
ADSP-2181/ADSP-2183 (C × VDD2 × f ) is calculated for each output: ADSP-2183 ENVIRONMENTAL CONDITIONS # of Pins × C Ambient Temperature Rating: TAMB = TCASE – (PD × θ CA) TCASE = Case Temperature in °C PD = Power Dissipation in W θ CA = Thermal Resistance (Case-to-Ambient) θ JA = Thermal Resistance (Junction-to-Ambient) θ JC = Thermal Resistance (Junction-to-Case) Package θJA Address, DMS Data Output, WR RD CLKOUT × 10 pF × 10 pF × 10 pF × 10 pF 8 9 1 1 × VDD2 ×f × 3.32 V × 3.32 V × 3.32 V × 3.
PAGE 19
ADSP-2181/ADSP-2183 ADSP-2183 from which t DIS = t MEASURED – t DECAY CAPACITIVE LOADING Figures 17 and 18 show the capacitive loading characteristics of the ADSP-2183. is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. 30 T = +85°C VDD = 3.0V INPUT 3.0V 1.5V 0.0V OUTPUT 2.0V 1.5V 0.3V RISE TIME (0.4V – 2.4V) – ns 25 20 15 Figure 19.
PAGE 20
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit 60 20 20 150 ns ns ns Clock Signals and Reset Timing Requirements: tCKI tCKIL tCKIH CLKIN Period CLKIN Width Low CLKIN Width High Switching Characteristics: tCKL tCKH tCKOH CLKOUT Width Low CLKOUT Width High CLKIN High to CLKOUT High 0.5tCK – 7 0.5tCK – 7 0 20 ns ns ns Control Signals Timing Requirements: tRSP RESET Width Low 5tCK1 ns ADSP-2183 28.8 MHz Parameter Min Max Unit 69.
PAGE 21
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit Interrupts and Flag Timing Requirements: tIFS tIFH IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25tCK + 15 0.25tCK Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 ns ns 0.5tCK – 7 0.25tCK + 5 ns ns Max Unit ADSP-2183 28.
PAGE 22
ADSP-2181/ADSP-2183 ADSP-2181/ADSP-2183 Parameter Min Max Unit Bus Request/Grant Timing Requirements: tBH tBS BR Hold after CLKOUT High1 BR Setup before CLKOUT Low1 0.25tCK + 2 0.25tCK + 17 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable tSDB xMS, RD, WR Disable to BG Low tSE BG High to xMS, RD, WR Enable tSEC xMS, RD, WR Enable to CLKOUT High tSDBH xMS, RD, WR Disable to BGH Low2 tSEH BGH High to xMS, RD, WR Enable2 ns ns 0.25tCK + 10 ns 0 ns 0 ns 0.
PAGE 23
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit 0.5tCK – 9 + w 0.75tCK – 10.5 + w ns ns ns Memory Read Timing Requirements: tRDD RD Low to Data Valid tAA A0-A13, xMS to Data Valid tRDH Data Hold from RD High 0 Switching Characteristics: RD Pulse Width tRP tCRD CLKOUT High to RD Low tASR A0-A13, xMS Setup before RD Low tRDA A0-A13, xMS Hold after RD Deasserted tRWR RD High to RD or WR Low 0.5tCK – 5 + w 0.25tCK – 5 0.25tCK – 6 0.25tCK – 3 0.5tCK – 5 0.25tCK + 7 ns ns ns ns ns ADSP-2183 28.
PAGE 24
ADSP-2181/ADSP-2183 ADSP-2181/ADSP-2183 Parameter Min Max Unit Memory Write Switching Characteristics: tDW Data Setup before WR High tDH Data Hold after WR High tWP WR Pulse Width tWDE WR Low to Data Enabled tASW A0-A13, xMS Setup before WR Low tDDR Data Disable before WR or RD Low tCWR CLKOUT High to WR Low tAW A0-A13, xMS, Setup before WR Deasserted tWRA A0-A13, xMS Hold after WR Deasserted tWWR WR High to RD or WR Low 0.5tCK – 7+ w 0.25tCK – 2 0.5tCK – 5 + w 0 0.25tCK – 6 0.25tCK – 7 0.25tCK – 5 0.
PAGE 25
ADSP-2181/ADSP-2183 ADSP-2181/ADSP-2183 Parameter Min Max Unit Serial Ports Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low tSCP SCLKIN Width 50 4 7 20 Switching Characteristics: tCC CLKOUT High to SCLKOUT tSCDE SCLK High to DT Enable tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold after SCLK High tRD TFS/RFSOUT Delay from SCLK High tSCDH DT Hold after SCLK High tTDE TFS (Alt) to DT Enable tTDV TFS (Alt) to DT Valid tSCDD SCLK High to DT
PAGE 26
ADSP-2181/ADSP-2183 ADSP-2181/ADSP-2183 Parameter Min Max Unit IDMA Address Latch Timing Requirements: tIALP Duration of Address Latch1, 3 tIASU IAD15–0 Address Setup before Address Latch End3 tIAH IAD15–0 Address Hold after Address Latch End3 tIKA IACK Low before Start of Address Latch1 tIALS Start of Write or Read after Address Latch End2, 3 10 5 2 0 3 ns ns ns ns ns NOTES 1 Start of Address Latch = IS Low and IAL High. 2 Start of Write or Read = IS Low and IWR Low or IRD Low.
PAGE 27
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit IDMA Write, Short Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIWP Duration of Write1, 2 tIDSU IAD15–0 Data Setup before End of Write2, 3, 4 tIDH IAD15–0 Data Hold after End of Write2, 3, 4 0 15 5 2 ns ns ns ns Switching Characteristics: tIKHW Start of Write to IACK High 15 ns Max Unit ADSP-2183 28.
PAGE 28
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit IDMA Write, Long Write Cycle Timing Requirements: tIKW IACK Low before Start of Write1 tIKSU IAD15–0 Data Setup before IACK Low2, 3 tIKH IAD15–0 Data Hold after IACK Low2, 3 0 0.5tCK + 10 2 Switching Characteristics: Start of Write to IACK Low4 tIKLW tIKHW Start of Write to IACK High ns ns ns 1.5tCK 15 ns ns Max Unit ADSP-2183 28.
PAGE 29
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRP Duration of Read 0 15 Switching Characteristics: IACK High after Start of Read1 tIKHR tIKDS IAD15–0 Data Setup before IACK Low tIKDH IAD15–0 Data Hold after End of Read2 tIKDD IAD15–0 Data Disabled after End of Read2 tIRDE IAD15–0 Previous Data Enabled after Start of Read tIRDV IAD15–0 Previous Data Valid after Start of Read tIRDH1 IAD15–0 Previous Data Hold aft
PAGE 30
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit IDMA Read, Short Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 tIRP Duration of Read 0 15 Switching Characteristics: tIKHR IACK High after Start of Read1 tIKDH IAD15–0 Data Hold after End of Read2 tIKDD IAD15–0 Data Disabled after End of Read2 tIRDE IAD15–0 Previous Data Enabled after Start of Read tIRDV IAD15–0 Previous Data Valid after Start of Read ns ns 15 0 10 0 15 ns ns ns ns ns ADSP-2183 Parameter 28.
PAGE 31
ADSP-2181/ADSP-2183 IS GND PF4 PF5 PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND VDD IAD6 IAD7 IAD8 IAD9 IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 IRD IWR 128-Lead TQFP Package Pinout 128 103 102 1 IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP PWD IRQ2 TOP VIEW (PINS DOWN) 38 65 64 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0 TFS1/IRQ1 RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET E
PAGE 32
ADSP-2181/ADSP-2183 TQFP Pin Configurations TQFP Number Pin Name TQFP Number Pin Name TQFP Number Pin Name TQFP Number Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A12 A13 IRQE MMAP PWD IRQ2 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQ
PAGE 33
ADSP-2181/ADSP-2183 OUTLINE DIMENSIONS 128-Lead Metric Thin Plastic Quad Flatpack (TQFP) D D1 D3 A L 103 102 128 1 SEATING PLANE TOP VIEW (PINS DOWN) 65 64 38 D E3 E1 E 39 A1 A2 SYMBOL B MILLIMETERS MIN TYP MAX A MIN 1.60 A1 0.05 A2 1.30 D D1 INCHES TYP MAX 0.063 0.15 0.002 1.40 1.50 0.051 0.055 0.059 15.75 16.00 16.25 0.620 0.630 0.640 13.90 14.00 14.10 0.547 0.551 0.555 12.50 12.58 0.492 0.495 D3 0.006 E 21.75 22.00 22.25 0.856 0.866 0.876 E1 19.
PAGE 34
ADSP-2181/ADSP-2183 PF1 PF2 PF3 IAL IS GND PF4 PF5 PF6 PF7 IAD0 IAD1 IAD2 IAD3 IAD4 IAD5 GND VDD IAD6 IAD7 IAD8 IAD9 IAD10 IAD11 IAD12 IAD13 IAD14 IAD15 IRD IWR GND D23 128-Lead PQFP Package Pinout 128 97 96 1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP D22 D21 D20 D19 D18 D17 D16 D15 GND VDD GND D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 GND D4 D3 D2 D1 D0 VDD 128L PQFP (28mm x 28mm) TOP VIEW (PINS DOWN) BG EBG BR EBR 32 65 33
PAGE 35
ADSP-2181/ADSP-2183 PQFP Pin Configurations PQFP Number Pin Name PQFP Number Pin Name PQFP Number Pin Name PQFP Number Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PWD IRQ2 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 D
PAGE 36
ADSP-2181/ADSP-2183 OUTLINE DIMENSIONS 128-Lead Metric Plastic Quad Flatpack (PQFP) D D1 D3 A L 128 1 SEATING PLANE 97 96 TOP VIEW (PINS DOWN) E3 E1 E 65 64 D 32 33 A1 A2 SYMBOL B MILLIMETERS MIN TYP MAX A e MIN INCHES TYP MAX 4.07 0.160 0.25 A2 3.17 3.49 3.67 0.125 0.137 0.144 D, E 30.95 31.20 31.45 1.219 1.228 1.238 D1, E 1 27.90 28.00 28.10 1.098 1.102 1.106 D3, E 3 24.73 24.80 24.87 0.974 0.976 0.979 L 0.65 0.88 1.03 0.031 0.035 0.041 e 0.73 0.
PAGE 37
ADSP-2181/ADSP-2183 ORDERING GUIDE Part Number Ambient Temperature Range Instruction Rate (MHz) Package Description Package Option* ADSP-2181KST-115 ADSP-2181BST-115 ADSP-2181KS-115 ADSP-2181BS-115 ADSP-2181KST-133 ADSP-2181BST-133 ADSP-2181KS-133 ADSP-2181BS-133 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 28.8 28.8 28.8 28.8 33.3 33.3 33.3 33.
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