Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 21 of 64 | August 2013
The following three tables describe the voltage/frequency
requirements for the processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock (Table 10 and Table 11) and system clock (Table 13)
specifications. Table 12 describes phase-locked loop operating
conditions.
Table 10. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
Parameter Internal Regulator Setting Max Unit
f
CCLK
CCLK Frequency (V
DDINT
= 1.3 V Minimum)
1
1.30 V 600 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.2 V Minimum)
2
1.25 V 533 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.14 V Minimum)
3
1.20 V 500 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.045 V Minimum) 1.10 V 444 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 400 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.85 V Minimum) 0.90 V 333 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 250 MHz
1
Applies to 600 MHz models only. See Ordering Guide on Page 63.
2
Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 63. 533 MHz models cannot support internal regulator levels above 1.25 V.
3
Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 63. 500 MHz models cannot support internal regulator levels above 1.20 V.
Table 11. Core Clock (CCLK) Requirements—400 MHz Models
1
Parameter
T
J
= 125°C All
2
Other T
J
UnitInternal Regulator Setting Max Max
f
CCLK
CCLK Frequency (V
DDINT
= 1.14 V Minimum) 1.20 V 400 400 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.045 V Minimum) 1.10 V 333 364 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 295 333 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.85 V Minimum) 0.90 V 280 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 250 MHz
1
See Ordering Guide on Page 63.
2
See Operating Conditions on Page 20.
Table 12. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency 50 Max f
CCLK
MHz
Table 13. System Clock (SCLK) Requirements
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter
1
Max Max Unit
CSP_BGA/PBGA
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
 1.14 V) 100 133 MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
 1.14 V) 100 100 MHz
LQFP
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
 1.14 V) 100 133 MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
 1.14 V) 83 83 MHz
1
t
SCLK
(= 1/f
SCLK
) must be greater than or equal to t
CCLK
.