Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 27 of 64 | August 2013
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 21 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 25, combinations of
CLKIN and clock multipliers/divisors must not result in core/
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Table 21. Clock and Reset Timing
Parameter Min Max Unit
Timing Requirements
t
CKIN
CLKIN Period
1, 2, 3, 4
25.0 100.0 ns
t
CKINL
CLKIN Low Pulse 10.0 ns
t
CKINH
CLKIN High Pulse 10.0 ns
t
WRST
RESET Asserted Pulse Width Low
5
11  t
CKIN
ns
t
NOBOOT
RESET Deassertion to First External Access Delay
6
3  t
CKIN
5  t
CKIN
ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
CLKIN frequency must not change on the fly.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 11 on Page 21 through
Table 13 on Page 21. Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4
If the DF bit in the PLL_CTL register is set, then the maximum t
CKIN
period is 50 ns.
5
Applies after power-up sequence is complete. See Table 22 and Figure 12 for power-up reset timing.
6
Applies when processor is configured in No Boot Mode (BMODE1-0 = b#00).
Figure 11. Clock and Reset Timing
Table 22. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirement
t
RST_IN_PWR
RESET Deasserted After the V
DDINT
, V
DDEXT
, V
DDRTC
, and CLKIN Pins Are Stable and
Within Specification
3500  t
CKIN
ns
In Figure 12, V
DD_SUPPLIES
is V
DDINT
, V
DDEXT
, V
DDRTC
Figure 12. Power-Up Reset Timing
CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
RESET
t
NOBOOT
RESET
t
RST_IN_PWR
CLKIN
V
DD_SUPPLIES