Datasheet

Rev. I | Page 28 of 64 | August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 23. Asynchronous Memory Read Cycle Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT 2.1 2.1 ns
t
HDAT
DATA15–0 Hold After CLKOUT 1.0 0.8 ns
t
SARDY
ARDY Setup Before CLKOUT 4.0 4.0 ns
t
HARDY
ARDY Hold After CLKOUT 1.0 0.0 ns
Switching Characteristics
t
DO
Output Delay After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.
6.0 6.0 ns
t
HO
Output Hold After CLKOUT
1
1.0 0.8 ns
Figure 13. Asynchronous Memory Read Cycle Timing
t
SARDY
t
HARDY
t
SARDY
t
HARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t
DO
t
HO
t
DO
t
SDAT
t
HDAT
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t
HO