Datasheet

Rev. I | Page 30 of 64 | August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 25. SDRAM Interface Timing
1
1
SDRAM timing for T
J
> 105°C is limited to 100 MHz.
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before CLKOUT 2.1 1.5 ns
t
HSDAT
DATA Hold After CLKOUT 0.8 0.8 ns
Switching Characteristics
t
DCAD
Command, ADDR, Data Delay After CLKOUT
2
2
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
6.0 4.0 ns
t
HCAD
Command, ADDR, Data Hold After CLKOUT
2
1.0 1.0 ns
t
DSDAT
Data Disable After CLKOUT 6.0 4.0 ns
t
ENSDAT
Data Enable After CLKOUT 1.0 1.0 ns
t
SCLK
CLKOUT Period
3
3
Refer to Table 13 on Page 21 for maximum f
SCLK
at various V
DDINT
.
10.0 7.5 ns
t
SCLKH
CLKOUT Width High 2.5 2.5 ns
t
SCLKL
CLKOUT Width Low 2.5 2.5 ns
Figure 15. SDRAM Interface Timing
t
SCLK
CLKOUT
t
SCLKL
t
SCLKH
t
SSDAT
t
HSDAT
t
ENSDAT
t
DCAD
t
DSDAT
t
HCAD
t
DCAD
t
HCAD
DATA (IN)
DATA (OUT)
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.