Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 31 of 64 | August 2013
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 16 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
V
DDEXT
= 1.8 V
CSP_BGA Package
V
DDEXT
= 2.5 V/3.3 V
All Packages
Parameter Min Max Min Max Min Max Unit
Timing Requirements
t
BS
BR Asserted to CLKOUT High Setup 4.6 4.6 4.6 ns
t
BH
CLKOUT High to BR Deasserted Hold Time 1.0 1.0 0.0 ns
Switching Characteristics
t
SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable 4.5 4.5 4.5 ns
t
SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable 4.5 4.5 4.5 ns
t
DBG
CLKOUT High to BG High Setup 6.0 5.5 3.6 ns
t
EBG
CLKOUT High to BG Deasserted Hold Time 6.0 4.6 3.6 ns
t
DBH
CLKOUT High to BGH High Setup 6.0 5.5 3.6 ns
t
EBH
CLKOUT High to BGH Deasserted Hold Time 6.0 4.6 3.6 ns
Figure 16. External Port Bus Request and Grant Cycle Timing
AMSx
CLKOUT
BG
BGH
BR
ADDR 19-1
ABE1-0
t
BH
t
BS
t
SD
t
SE
t
SD
t
SD
t
SE
t
SE
t
EBG
t
DBG
t
EBH
t
DBH
AWE
ARE