Datasheet

Rev. I | Page 32 of 64 | August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 27 and Figure 17 through Figure 22 describe parallel
peripheral interface operations.
Table 27. Parallel Peripheral Interface Timing
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
V
DDEXT
= 1.8 V
CSP_BGA Package
V
DDEXT
= 2.5 V/3.3 V
All Packages
Parameter Min Max Min Max Min Max Unit
Timing Requirements
t
PCLKW
PPI_CLK Width 8.0 8.0 6.0 ns
t
PCLK
PPI_CLK Period
1
20.0 20.0 15.0 ns
t
SFSPE
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
6.0 6.0 4.0
2
ns
ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.0
2
1.0
2
1.0
2
ns
t
SDRPE
Receive Data Setup Before PPI_CLK 3.5 3.5 3.5 ns
t
HDRPE
Receive Data Hold After PPI_CLK 1.5 1.5 1.5 ns
Switching Characteristics—GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 11.0 8.0 8.0 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 1.7 1.7 1.7 ns
t
DDTPE
Transmit Data Delay After PPI_CLK 11.0 9.0 9.0 ns
t
HDTPE
Transmit Data Hold After PPI_CLK 1.8 1.8 1.8 ns
1
PPI_CLK frequency cannot exceed f
SCLK
/2.
2
Applies when PPI_CONTROL Bit 8 is cleared. See Figure 19 and Figure 22.
Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
t
HDRPE
t
SDRPE
t
HOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
DFSPE
t
PCLK
t
PCLKW
t
PCLK
t
SFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
HDRPE
t
SDRPE
t
PCLKW