Datasheet

Rev. I | Page 34 of 64 | August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Port Timing
Table 28 through Table 31 on Page 37 and Figure 23 on Page 35
through Figure 26 on Page 37 describe Serial Port operations.
Table 28. Serial Ports—External Clock
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
3.0 3.0 ns
t
HFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
3.0 3.0 ns
t
SDRE
Receive Data Setup Before RSCLKx
1
3.0 3.0 ns
t
HDRE
Receive Data Hold After RSCLKx
1
3.0 3.0 ns
t
SCLKEW
TSCLKx/RSCLKx Width 8.0 4.5 ns
t
SCLKE
TSCLKx/RSCLKx Period 20.0 15.0
2
ns
t
SUDTE
Start-Up Delay From SPORT Enable To First External TFSx
3
4.0 × t
SCLKE
4.0 × t
SCLKE
ns
t
SUDRE
Start-Up Delay From SPORT Enable To First External RFSx
3
4.0 × t
SCLKE
4.0 × t
SCLKE
ns
Switching Characteristics
t
DFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
4
10.0 10.0 ns
t
HOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
1
0.0 0.0 ns
t
DDTE
Transmit Data Delay After TSCLKx
1
10.0 10.0 ns
t
HDTE
Transmit Data Hold After TSCLKx
1
0.0 0.0 ns
1
Referenced to sample edge.
2
For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3
Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
4
Referenced to drive edge.
Table 29. Serial Ports—Internal Clock
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.0 9.0 ns
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
2.0 2.0 ns
t
SDRI
Receive Data Setup Before RSCLKx
1
9.5 9.0 ns
t
HDRI
Receive Data Hold After RSCLKx
1
0.0 0.0 ns
Switching Characteristics
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
3.0 3.0 ns
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
1
1.0 1.0 ns
t
DDTI
Transmit Data Delay After TSCLKx
1
3.0 3.0 ns
t
HDTI
Transmit Data Hold After TSCLKx
1
2.5 2.0 ns
t
SCLKIW
TSCLKx/RSCLKx Width 6.0 4.5 ns
1
Referenced to sample edge.
2
Referenced to drive edge.