Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 37 of 64 | August 2013
Table 31. External Late Frame Sync
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
V
DDEXT
= 1.8 V
CSP_BGA Package
V
DDEXT
= 2.5 V/3.3 V
All Packages
Parameter Min Max Min Max Min Max Unit
Switching Characteristics
t
DDTLFSE
D at a D e l ay f r om L a te E x t e rn a l T F Sx o r E x te r n a l R F S x
in multichannel mode with MCMEN = 0
1, 2
10.5 10.0 10.0 ns
t
DTENLFS
Data Enable from Late FS or in multichannel mode
with MCMEN = 0
1, 2
000ns
1
In multichannel mode, TFSx enable and TFSx valid follow t
DTENLFS
and t
DDTLFSE
.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > t
SCLKE
/2, then t
DDTTE/I
and t
DTENE/I
apply; otherwise t
DDTLFSE
and t
DTENLFS
apply.
Figure 26. External Late Frame Sync
RSCLKx
RFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
EXTERNAL RFSx IN MULTI-CHANNEL MODE
1ST BIT
t
DTENLFSE
t
DDTLFSE
TSCLKx
TFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
LATE EXTERNAL TFSx
1ST BIT
t
DDTLFSE