Datasheet

Rev. I | Page 38 of 64 | August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port—Master Timing
Table 32. Serial Peripheral Interface (SPI) Port—Master Timing
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
V
DDEXT
= 1.8 V
CSP_BGA Package
V
DDEXT
= 2.5 V/3.3 V
All Packages
Parameter Min Max Min Max Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup) 10.5 9 7.5 ns
t
HSPIDM
SCK Sampling Edge to Data Input Invalid –1.5 –1.5 –1.5 ns
Switching Characteristics
t
SDSCIM
SPISELx Low to First SCK Edge 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICHM
Serial Clock High Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICLM
Serial Clock Low Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
– 1.5 4 × t
SCLK
– 1.5 4 × t
SCLK
– 1.5 ns
t
HDSM
Last SCK Edge to SPISELx High 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPITDM
Sequential Transfer Delay 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay) 6 6 6 ns
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold) –1.0 –1.0 –1.0 ns
Figure 27. Serial Peripheral Interface (SPI) Port—Master Timing
t
SDSCIM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
t
HDSPIDM
t
HSPIDM
t
SSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
t
DDSPIDM
t
HSPIDM
t
SSPIDM
t
HDSPIDM
t
DDSPIDM