Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 39 of 64 | August 2013
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing
V
DDEXT
= 1.8 V
LQFP/PBGA Packages
V
DDEXT
= 1.8 V
CSP_BGA Package
V
DDEXT
= 2.5 V/3.3 V
All Packages
Parameter Min Max Min Max Min Max Unit
Timing Requirements
t
SPICHS
Serial Clock High Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLS
Serial Clock Low Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
4 × t
SCLK
4 × t
SCLK
ns
t
HDS
Last SCK Edge to SPISS Not Asserted 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPITDS
Sequential Transfer Delay 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SDSCI
SPISS Assertion to First SCK Edge 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 1.6 ns
t
HSPID
SCK Sampling Edge to Data Input Invalid 1.6 1.6 1.6 ns
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active 0 10 0 9 0 8 ns
t
DSDHI
SPISS Deassertion to Data High Impedance 0 10 0 9 0 8 ns
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay) 10 10 10 ns
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold) 0 0 0 ns
Figure 28. Serial Peripheral Interface (SPI) Port—Slave Timing
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
DDSPID
t
DSDHI
t
HDSPID
t
SSPID
t
DSDHI
t
HDSPID
t
DSOE
t
HSPID
t
SSPID
t
DDSPID
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
CPHA = 1
CPHA = 0
t
HSPID