Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 41 of 64 | August 2013
Timer Clock Timing
Table 35 and Figure 30 describe timer clock timing.
Timer Cycle Timing
Table 36 and Figure 31 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f
SCLK
/2 MHz.
Table 35. Timer Clock Timing
Parameter Min Max Unit
Switching Characteristic
t
TODP
Timer Output Update Delay After PPI_CLK High 12 ns
Figure 30. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
t
TODP
Table 36. Timer Cycle Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Characteristics
t
WL
Timer Pulse Width Low
1
1 × t
SCLK
1 × t
SCLK
ns
t
WH
Timer Pulse Width High
1
1 × t
SCLK
1 × t
SCLK
ns
t
TIS
Timer Input Setup Time Before CLKOUT Low
2
8.0 6.5 ns
t
TIH
Timer Input Hold Time After CLKOUT Low
2
1.5 1.5 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output 1 × t
SCLK
(2
32
–1) × t
SCLK
1 × t
SCLK
(2
32
–1) × t
SCLK
ns
t
TOD
Timer Output Update Delay After CLKOUT High 7.5 6.5 ns
1
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 31. Timer PWM_OUT Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
t
TIS
t
TIH
t
WH
,t
WL
t
TOD
t
HTO