Datasheet

Rev. I | Page 42 of 64 | August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 37. JTAG Port Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 4 ns
t
SSYS
System Inputs Setup Before TCK High
1
1
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PPI3–0.
44 ns
t
HSYS
System Inputs Hold After TCK High
1
55 ns
t
TRSTW
TRST Pulse Width
2
(Measured in TCK Cycles)
2
50 MHz maximum.
44 TCK
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 10 ns
t
DSYS
System Outputs Delay After TCK Low
3
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
012012ns
Figure 32. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS