Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 13 of 104
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter Min Typ Max Unit
CLK
1
UCLK
t
MS_AFTER_CLKH
0 4 ns
t
ADDR_AFTER_CLKH
4 8 ns
t
AE_H_AFTER_MS
½ CLK
t
AE
(XMxPAR[14:12] + 1) × CLK
t
HOLD_ADDR_AFTER_AE_L
½ CLK + (!XMxPAR[10]) × CLK
t
HOLD_ADDR_BEFORE_WR_L
(!XMxPAR[8]) × CLK
t
WR_L_AFTER_AE_L
½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK
t
DATA_AFTER_WR_L
8 12 ns
t
WR
(XMxPAR[7:4] + 1) × CLK
t
WR_H_AFTER_CLKH
0 4 ns
t
HOLD_DATA_AFTER_WR_H
(!XMxPAR[8]) × CLK
t
BEN_AFTER_AE_L
½ CLK
t
RELEASE_MS_AFTER_WR_H
(!XMxPAR[8] + 1) × CLK
1
See Table 78.
04955-052
CLK
CLK
t
MS_AFTER_CLKH
t
AE_H_AFTER_MS
t
AE
t
WR_L_AFTER_A E_L
MSx
AE
WS
RS
AD[16:1] FFFF 9ABC 5678 9ABE 1234
BLE
BHE
A16
t
WR
t
WR_H_AFTER_CLKH
t
HOLD_DATA_AFTER_WR_H
t
HOLD_ADDR_AFTER_AE_L
t
HOLD_ADDR_BEFORE_WR_L
t
DATA_AFTER_WR_L
t
BEN_AFTER_AE_L
t
ADDR_AFTER_CLKH
t
RELEASE _MS_AFTER_WR_H
Figure 12. External Memory Write Cycle (See Table 78)