Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 14 of 104
Table 3. External Memory Read Cycle
Parameter Min Typ Max Unit
CLK
1
1/MD clock ns typ × (POWCON[2:0] + 1)
t
MS_AFTER_CLKH
4 8 ns
t
ADDR_AFTER_CLKH
4 16 ns
t
AE_H_AFTER_MS
½ CLK
t
AE
(XMxPAR[14:12] + 1) × CLK
t
HOLD_ADDR_AFTER_AE_L
½ CLK + (! XMxPAR[10] ) × CLK
t
RD_L_AFTER_AE_L
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
t
RD_H_AFTER_CLKH
0 4
t
RD
(XMxPAR[3:0] + 1) × CLK
t
DATA_BEFORE_RD_H
16 ns
t
DATA_AFTER_RD_H
8 + (! XMxPAR[9]) × CLK
t
RELEASE_MS_AFTER_RD_H
1 × CLK
1
See Table 78.
04955-053
ECLK
MSx
AE
WS
RS
AD[16:1]
BHE
BLE
A16
FFFF 2348 XXXX CDEF XX 234A XX 89AB
CLK
t
AE_H_AFTER_MS
t
AE
t
HOLD_ADDR_AFTER_AE_L
t
RD_L_AFTER_AE_L
t
RD
t
RD_H_AFTER_CLKH
t
ADDR_AFTER_CLKH
t
RELEASE_MS_AFTER_RD_H
t
DATA_BEFORE_RD_H
t
DATA_AFTER_RD _H
t
MS_AFTER_CLKH
Figure 13. External Memory Read Cycle (See Table 78)