Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 15 of 104
Table 4. I
2
C Timing in Fast Mode (400 kHz)
Slave Master
Parameter Description Min Max Typ Unit
t
L
SCL low pulse width
1
200 1360 ns
t
H
SCL high pulse width
1
100 1140 ns
t
SHD
Start condition hold time 300 ns
t
DSU
Data setup time 100 740 ns
t
DHD
Data hold time 0 400 ns
t
RSU
Setup time for repeated start 100 ns
t
PSU
Stop condition setup time 100 400 ns
t
BUF
Bus-free time between a stop condition and a start condition 1.3
s
t
R
Rise time for both SCL and SDA 300 200 ns
t
F
Fall time for both SCL and SDA 300 ns
t
SUP
Pulse width of spike suppressed 50 ns
1
t
HCLK
depends on the clock divider or CD bits in the POWCON MMR. t
HCLK
= t
UCLK
/2
CD
; see Figure 67.
Table 5. I
2
C Timing in Standard Mode (100 kHz)
Slave Master
Parameter Description Min Max Typ Unit
t
L
SCL low pulse width
1
4.7 μs
t
H
SCL high pulse width
1
4.0 ns
t
SHD
Start condition hold time 4.0 μs
t
DSU
Data setup time 250 ns
t
DHD
Data hold time 0 3.45 μs
t
RSU
Setup time for repeated start 4.7 μs
t
PSU
Stop condition setup time 4.0 μs
t
BUF
Bus-free time between a stop condition and a start condition 4.7 μs
t
R
Rise time for both SCL and SDA 1 μs
t
F
Fall time for both SCL and SDA 300 ns
1
t
HCLK
depends on the clock divider or CD bits in the POWCON MMR. t
HCLK
= t
UCLK
/2
CD
; see Figure 67.
0
4955-054
SDA (I/O)
t
BUF
MSB LSB ACK MSB
1982–71
SCL (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
t
SUP
t
R
t
F
t
F
t
R
t
H
t
L
t
SUP
t
DSU
t
DHD
t
RSU
t
DHD
t
DSU
t
SHD
t
PSU
Figure 14. I
2
C Compatible Interface Timing