Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 16 of 104
Table 6. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
HCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge
2
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLK edge
2
2 × t
UCLK
ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SR
SCLK rise time 5 12.5 ns
t
SF
SCLK fall time 5 12.5 ns
1
t
HCLK
depends on the clock divider or CD bits in the POWCONMMR. t
HCLK
= t
UCLK
/2
CD
; see Figure 67.
2
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
0
4955-055
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
Figure 15. SPI Master Mode Timing (Phase Mode = 1)