Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 19 of 104
Table 9. SPI Slave Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
t
CS
CS
to SCLK edge
1
(2 × t
HCLK
) + (2 × t
UCLK
) ns
t
SL
SCLK low pulse width
2
(SPIDIV + 1) × t
HCLK
ns
t
SH
SCLK high pulse width
2
(SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SR
SCLK rise time 5 12.5 ns
t
SF
SCLK fall time 5 12.5 ns
t
DOCS
Data output valid after CS
edge
25 ns
t
SFS
CS
high after SCLK edge
0 ns
1
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 67.
2
t
HCLK
depends on the clock divider or CD bits in the POWCONMMR. t
HCLK
= t
UCLK
/2
CD
; see Figure 67.
04955-058
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO
MOSI
MSB IN BITS 6 TO 1 LSB IN
t
DHD
t
DSU
MSB BITS 6 TO 1 LSB
t
DOCS
t
DAV
t
DR
t
DF
t
CS
Figure 18. SPI Slave Mode Timing (Phase Mode = 0)