Datasheet
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 23 of 104
Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020 7021 7022 Mnemonic Description
38 37 36 ADC0 Single-Ended or Differential Analog Input 0.
39 38 37 ADC1 Single-Ended or Differential Analog Input 1.
40 39 38 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
1 40 39 ADC3/CMP1 Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/
Comparator Negative Input.
2 1 40 ADC4 Single-Ended or Differential Analog Input 4.
‒
2 1 ADC5 Single-Ended or Differential Analog Input 5.
‒
3 2 ADC6 Single-Ended or Differential Analog Input 6.
‒
4 3 ADC7 Single-Ended or Differential Analog Input 7.
‒ ‒
4 ADC8 Single-Ended or Differential Analog Input 8.
‒ ‒
5
ADC9
Single-Ended or Differential Analog Input 9.
3 5 6 GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4
6
‒
DAC0/ADC12
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
5 7
‒
DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
6
‒ ‒
DAC2/ADC14 DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
7
‒ ‒
DAC3/ADC15
DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
must be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15 (see
Figure 53).
8 8 7 TMS Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOV
DD
. In some cases, an external
pull-up resistor (~100K) is also required to ensure that the part does not
enter an erroneous state.
9 9 8 TDI Test Data In, JTAG Test Port Input. Debug and download access.
10 10 9 BM/P0.0/CMP
OUT
/PLAI[7] Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter
serial download mode if BM is low at reset and execute code if BM is
pulled high at reset through a 1 kΩ resistor/General-Purpose Input and
Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
11 11 10 P0.6/T1/MRST/PLAO[3] Multifunction Pin. Driven low after reset. General-Purpose Output Port 0.6/
Timer1 Input/Power-On Reset Output/Programmable Logic Array Output
Element 3.
12 12 11 TCK Test Clock, JTAG Test Port Input. Debug and download access. This pin has
an internal pull-up resistor to IOV
DD
. In some cases an external pull-up
resistor (~100K) is also required to ensure that the part does not enter an
erroneous state.
13 13 12 TDO Test Data Out, JTAG Test Port Output. Debug and download access.
14 14 13 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
15 15 14 IOV
DD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage
Regulator.
16 16 15 LV
DD
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 µF capacitor to DGND only.
17 17 16 DGND Ground for Core Logic.
18 18 17 P0.3/TRST/ADC
BUSY
General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/
ADC
BUSY
Signal Output.
19 19 18
RST
Reset Input, Active Low.
20 20 19 IRQ0/P0.4/PWM
TRIP
/PLAO[1] Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable
Logic Array Output Element 1.
21 21 20 IRQ1/P0.5/ADC
BUSY
/PLAO[2] Multifunction I/O Pin. External Interrupt Request 1, Active High/General-
Purpose Input and Output Port 0.5/ADC
BUSY
Signal Output/Programmable
Logic Array Output Element 2.