Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 24 of 104
Pin No.
7019/7020 7021 7022 Mnemonic Description
22 22 21 P2.0/SPM9/PLAO[5]/
CONV
START
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/
Programmable Logic Array Output Element 5/Start Conversion Input Signal
for ADC.
23 23 22 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/
Output for External Clock Signal/Input to the Internal Clock Generator
Circuits/UART/ Programmable Logic Array Output Element 4.
24 24 23 XCLKO Output from the Crystal Oscillator Inverter.
25 25 24 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits.
26 26 25 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART,
SPI/Programmable Logic Array Output Element 0.
27
27
26
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART,
SPI/Programmable Logic Array Input Element 6.
28 28 27 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART,
SPI/Programmable Logic Array Input Element 5/External Interrupt
Request 3, Active High.
29 29 28 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART,
SPI/Programmable Logic Array Input Element 4/External Interrupt
Request 2, Active High.
30 30 29 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART,
I2C1/Programmable Logic Array Input Element 3.
31 31 30 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART,
I2C1/Programmable Logic Array Input Element 2.
32 32 31 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART,
I2C0/Programmable Logic Array Input Element 1.
33 33 32 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/
Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0.
34
‒ ‒
P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array
Output Element 10.
35 34 33 V
REF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 µF capacitor
when using the internal reference.
36 35 34 AGND Analog Ground. Ground reference point for the analog circuitry.
37 36 35 AV
DD
3.3 V Analog Power.
0 0 0 EP Exposed Pad. The pin configuration for the ADuC7019/ADuC7020/
ADuC7021/ADuC7022 has an exposed pad that must be soldered for
mechanical purposes and left unconnected.