Datasheet
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 28 of 104
ADuC7026/ADuC7027
04955-069
1ADC4
2ADC5
3ADC6
4ADC7
5ADC8
6ADC9
7ADC10
8GND
REF
9ADCNEG
10DAC0/ADC12
11DAC1/ADC13
12DAC2/ADC14
13DAC3/ADC15
14TMS
15TDI
16P0.1/PWM2
H
/BLE
17P2.3/AE
18P4.6/AD14/PLAO[14]
19P4.7/AD15/PLAO[15]
20BM/P0.0/CMP
OUT
/PLAI[7]/MS0
60 P1.2/SPM2/PLAI[2]
59 P1.3/SPM3/PLAI[3]
58 P1.4/SPM4/PLAI[4]/IRQ2
57 P1.5/SPM5/PLAI[5]/IRQ3
56 P4.1/AD9/PLAO[9]
55 P4.0/AD8/PLAO[8]
54 IOV
DD
53 IOGND
52 P1.6/SPM6/PLAI[6]
51 P1.7/SPM7/PLAO[0]
50 P2.2/RS/PWM0
L
/PLAO[7]
49 P2.1/WS/PWM0
H
/PLAO[6]
48 P2.7/PWM1
L
/MS3
47 P3.7/AD7/PWM
SYNC
/PLAI[15]
46 P3.6/AD6/PWM
TRIP
/PLAI[14]
45 XCLKI
44 XCLKO
43 P0.7/ECLK/XCLK/SPM8/PLAO[4]
42 P2.0/SPM9/PLAO[5]/CONV
START
41 IRQ1/P0.5/ADC
BUSY
/PLAO[2]/MS2
21P0.6/T1/MRST/PLAO[3]
22TCK
23TDO
24P0.2/PWM2
L
/BHE
25IOGND
26IOV
DD
27LV
DD
28DGND
29P3.0/AD0/PWM0
H
/PLAI[8]
30P3.1/AD1/PWM0
L
/PLAI[9]
31P3.2/AD2/PWM1
H
/PLAI[10]
32P3.3/AD3/PWM1
L
/PLAI[11]
33P2.4/PWM0
H
/MS0
34P0.3/TRST/A16/ADC
BUSY
35P2.5/PWM0
L
/MS1
36P2.6/PWM1
H
/MS2
37RST
38P3.4/AD4/PWM2
H
/PLAI[12]
39P3.5/AD5/PWM2
L
/PLAI[13]
40IRQ0/P0.4/PWM
TRIP
/PLAO[1]/MS1
80 ADC3/CMP1
79 ADC2/CMP0
78 ADC1
77 ADC0
76 ADC11
75 DACV
DD
74 AV
DD
73 AV
DD
72 AGND
71 AGND
70 DACGND
69 DAC
REF
68 V
REF
67 REFGND
66 P4.5/AD13/PLAO[13]
65 P4.4/AD12/PLAO[12]
64 P4.3/AD11/PLAO[11]
63 P4.2/AD10/PLAO[10]
62 P1.0/T1/SPM0/PLAI[0]
61 P1.1/SPM1/PLAI[1]
TOP VIEW
(Not to Scale)
ADuC7026/
ADuC7027
PIN 1
INDICATOR
Figure 25. 80-Lead LQFP Pin Configuration (ADuC7026/ADuC7027)
Table 13. Pin Function Descriptions (ADuC7026/ADuC7027)
Pin No. Mnemonic Description
1 ADC4 Single-Ended or Differential Analog Input 4.
2 ADC5 Single-Ended or Differential Analog Input 5.
3 ADC6 Single-Ended or Differential Analog Input 6.
4 ADC7 Single-Ended or Differential Analog Input 7.
5 ADC8 Single-Ended or Differential Analog Input 8.
6 ADC9 Single-Ended or Differential Analog Input 9.
7
ADC10
Single-Ended or Differential Analog Input 10.
8 GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
9 ADCNEG Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
10 DAC0/ADC12 DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7027.
11 DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7027.
12 DAC2/ADC14 DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not
present on the ADuC7027.
13
DAC3/ADC15
DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not
present on the ADuC7027.
14 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
15 TDI JTAG Test Port Input, Test Data In. Debug and download access.
16 P0.1/PWM2
H
/
BLE
General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
Byte Low Enable.
17 P2.3/AE General-Purpose Input and Output Port 2.3/External Memory Access Enable.