Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 34 of 104
Ball No. Mnemonic Description
E1 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
E2 BM/P0.0/CMP
OUT
/PLAI[7] Multifunction I/O Pin. Boot mode. The ADuC7029 enters UART download mode if BM is low
at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
E3 DAC2/ADC14 DAC2 Voltage Output/ADC Input 14.
E4 IOV
DD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
E5 P3.2/PWM1
H
/PLAI[10] General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
E6 P3.5/PWM2
L
/PLAI[13] General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
E7 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External
Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array
Output Element 4.
F1 TDI JTAG Test Port Input, Test Data In. Debug and download access.
F2 P0.6/T1/MRST/PLAO[3] Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
F3 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
F4 P3.1/PWM0
L
/PLAI[9] General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
F5 P3.0/PWM0
H
/PLAI[8] General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
F6
RST
Reset Input, Active Low.
F7 P2.0/SPM9/PLAO[5]/
CONV
START
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable
Logic Array Output Element 5/Start Conversion Input Signal for ADC.
G1 TCK JTAG Test Port Input, Test Clock. Debug and download access.
G2 TDO JTAG Test Port Output, Test Data Out. Debug and download access.
G3 LV
DD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 µF
capacitor to DGND only.
G4 DGND Ground for Core Logic.
G5 P0.3/TRST/ADC
BUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
BUSY
Signal
Output.
G6 IRQ0/P0.4/PWM
TRIP
/PLAO[1] Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
G7 IRQ1/P0.5/ADC
BUSY
/PLAO[2] Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
BUSY
Signal Output/Programmable Logic Array Output Element 2.