Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 56 of 104
OTHER ANALOG PERIPHERALS
DAC
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two,
three, or four 12-bit voltage output DACs on-chip, depending on
the model. Each DAC has a rail-to-rail voltage output buffer
capable of driving 5 kΩ/100 pF.
Each DAC has three selectable ranges: 0 V to V
REF
(internal
band gap 2.5 V reference), 0 V to DAC
REF
, and 0 V to AV
DD
.
DAC
REF
is equivalent to an external reference for the DAC.
The signal range is 0 V to AV
DD
.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 50) and DAC0DAT
(see Table 52) are described in detail in this section.
Table 49. DACxCON Registers
Name Address Default Value Access
DAC0CON 0xFFFF0600 0x00 R/W
DAC1CON 0xFFFF0608 0x00 R/W
DAC2CON 0xFFFF0610 0x00 R/W
DAC3CON 0xFFFF0618 0x00 R/W
Table 50. DAC0CON MMR Bit Designations
Bit Name Value Description
7:6 Reserved.
5 DACCLK
DAC update rate. Set by user to
update the DAC using Timer1.
Cleared by user to update the DAC
using HCLK (core clock).
4 DACCLR
DAC clear bit. Set by user to enable
normal DAC operation. Cleared by
user to reset data register of the DAC
to 0.
3 Reserved. This bit should be left at 0.
2 Reserved. This bit should be left at 0.
1:0 DAC range bits.
00
Power-down mode. The DAC output is
in three-state.
01 0 V to DAC
REF
range.
10 0 V to V
REF
(2.5 V) range.
11 0 V to AV
DD
range.
Table 51. DACxDAT Registers
Name Address Default Value Access
DAC0DAT 0xFFFF0604 0x00000000 R/W
DAC1DAT 0xFFFF060C 0x00000000 R/W
DAC2DAT 0xFFFF0614 0x00000000 R/W
DAC3DAT 0xFFFF061C 0x00000000 R/W
Table 52. DAC0DAT MMR Bit Designations
Bit Description
31:28 Reserved.
27:16 12-bit data for DAC0.
15:0 Reserved.
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 63.
04955-023
R
R
R
R
R
DAC0
V
REF
AV
DD
DAC
REF
Figure 63. DAC Structure
As illustrated in Figure 63, the reference source for each DAC is
user-selectable in software. It can be AV
DD
, V
REF
, or DAC
REF
. In
0-to-AV
DD
mode, the DAC output transfer function spans from
0 V to the voltage at the AV
DD
pin. In 0-to-DAC
REF
mode, the
DAC output transfer function spans from 0 V to the voltage at the
DAC
REF
pin. In 0-to-V
REF
mode, the DAC output transfer function
spans from 0 V to the internal 2.5 V reference, V
REF
.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
DD
and ground. Moreover, the DAC’s linearity specification
(when driving a 5 k resistive load to ground) is guaranteed
through the full transfer function, except Code 0 to Code 100,
and, in 0-to-AV
DD
mode only, Code 3995 to Code 4095.