Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 58 of 104
Input offset voltage (V
OS
) is the difference between the center of
the hysteresis range and the ground level. This can either be
positive or negative. The hysteresis voltage (V
H
) is one-half the
width of the hysteresis range.
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 56.
Table 55. CMPCON Register
Name Address Default Value Access
CMPCON 0xFFFF0444 0x0000 R/W
Table 56. CMPCON MMR Bit Descriptions
Bit Name Value Description
15:11 Reserved.
10 CMPEN Comparator enable bit. Set by user
to enable the comparator. Cleared
by user to disable the comparator.
9:8 CMPIN Comparator negative input
select bits.
00 AV
DD
/2.
01
ADC3 input.
10 DAC0 output.
11 Reserved.
7:6 CMPOC Comparator output configuration
bits.
00 Reserved.
01
Reserved.
10 Output on CMP
OUT
.
11 IRQ.
5 CMPOL Comparator output logic state bit.
When low, the comparator output
is high if the positive input (CMP0)
is above the negative input (CMP1).
When high, the comparator output
is high if the positive input is below
the negative input.
4:3 CMPRES Response time.
00 5 µs response time is typical for
large signals (2.5 V differential).
17 µs response time is typical for
small signals (0.65 mV differential).
11 3 µs typical.
01/10 Reserved.
2
CMPHYST
Comparator hysteresis bit. Set by
user to have a hysteresis of about
7.5 mV. Cleared by user to have no
hysteresis.
1 CMPORI Comparator output rising edge
interrupt. Set automatically when a
rising edge occurs on the moni-
tored voltage (CMP0). Cleared by
user by writing a 1 to this bit.
0 CMPOFI Comparator output falling edge
interrupt. Set automatically when a
falling edge occurs on the monitored
voltage (CMP0). Cleared by user.
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7019/20/21/22/24/25/26/27/28/29 integrates a
32.768 kHz ±3% oscillator, a clock divider, and a PLL. The PLL
locks onto a multiple (1275) of the internal oscillator or an external
32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for
the system. To allow power saving, the core can operate at this
frequency, or at binary submultiples of it. The actual core oper-
ating frequency, UCLK/2
CD
, is refered to as HCLK. The default
core clock is the PLL clock divided by 8 (CD = 3) or 5.22 MHz.
The core clock frequency can also come from an external clock
on the ECLK pin as described in Figure 67. The core clock can
be outputted on ECLK when using an internal oscillator or
external crystal.
Note that when the ECLK pin is used to output the core clock,
the output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
04955-026
*32.768kHz ±3%
AT POWER-UP
41.78MHz
OCLK
32.768kHz
WATCHDOG
TIMER
INT. 32kHz*
OSCILLATOR
CRYSTAL
OSCILLATOR
WAKE-UP
TIMER
MDCLK
HCLK
PLL
CORE
I
2
C
UCLK
ANALOG
PERIPHERALS
/2
CD
CD
XCLKO
XCLKI
P0.7/XCLK
P0.7/ECLK
Figure 67. Clocking System
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
External Crystal Selection
To switch to an external crystal, the user must do the following:
1. Enable the Timer2 interrupt and configure it for a timeout
period of >120 µs.
2. Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
3. Force the part into NAP mode by following the correct
write sequence to the POWCON register.
When the part is interrupted from NAP mode by the
Timer2 interrupt source, the clock source has switched to
the external clock.