Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 60 of 104
MMRs and Keys
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs: PLLCON (see Table 61)
and POWCON (see Table 64). PLLCON controls the operating
mode of the clock system, whereas POWCON controls the core
clock frequency and the power-down mode.
To prevent accidental programming, a certain sequence (see
Table 65) must be followed to write to the PLLCON and
POWCON registers.
Table 59. PLLKEYx Registers
Name
Address
Default Value
Access
PLLKEY1 0xFFFF0410 0x0000 W
PLLKEY2 0xFFFF0418 0x0000 W
Table 60. PLLCON Register
Name Address Default Value Access
PLLCON 0xFFFF0414 0x21 R/W
Table 61. PLLCON MMR Bit Designations
Bit
Name
Value
Description
7:6 Reserved.
5 OSEL 32 kHz PLL input selection. Set by
user to select the internal 32 kHz
oscillator. Set by default. Cleared by
user to select the external 32 kHz crystal.
4:2 Reserved.
1:0 MDCLK Clocking modes.
00
Reserved.
01 PLL. Default configuration.
10 Reserved.
11 External clock on the P0.7 pin.
Table 62. POWKEYx Registers
Name Address Default Value Access
POWKEY1 0xFFFF0404 0x0000 W
POWKEY2 0xFFFF040C 0x0000 W
Table 63. POWCON Register
Name Address Default Value Access
POWCON 0xFFFF0408 0x0003 R/W
Table 64. POWCON MMR Bit Designations
Bit Name Value Description
7 Reserved.
6:4 PC Operating modes.
000 Active mode.
001 Pause mode.
010 Nap.
011 Sleep mode. IRQ0 to IRQ3 and Timer2
can wake up the part.
100 Stop mode. IRQ0 to IRQ3 can wake up
the part.
Others Reserved.
3 Reserved.
2:0 CD CPU clock divider bits.
000 41.78 MHz.
001 20.89 MHz.
010
10.44 MHz.
011 5.22 MHz.
100 2.61 MHz.
101 1.31 MHz.
110 653 kHz.
111 326 kHz.
Table 65. PLLCON and POWCON Write Sequence
PLLCON POWCON
PLLKEY1 = 0xAA POWKEY1 = 0x01
PLLCON = 0x01 POWCON = user value
PLLKEY2 = 0x55 POWKEY2 = 0xF4