Datasheet

ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. F | Page 70 of 104
Table 85. GPxDAT Registers
Name Address Default Value
1
Access
GP0DAT 0xFFFFF420 0x000000XX R/W
GP1DAT
0xFFFFF430
0x000000XX
R/W
GP2DAT 0xFFFFF440 0x000000XX R/W
GP3DAT 0xFFFFF450 0x000000XX R/W
GP4DAT 0xFFFFF460 0x000000XX R/W
1
X = 0, 1, 2, or 3.
GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins configured as output, and store the
input value of the pins configured as input.
Table 86. GPxDAT MMR Bit Descriptions
Bit Description
31:24 Direction of the data. Set to 1 by user to configure
the GPIO pin as an output. Cleared to 0 by user to
configure the GPIO pin as an input.
23:16 Port x data output.
15:8 Reflect the state of Port x pins at reset (read only).
7:0 Port x data input (read only).
Table 87. GPxSET Registers
Name Address Default Value
1
Access
GP0SET 0xFFFFF424 0x000000XX W
GP1SET 0xFFFFF434 0x000000XX W
GP2SET 0xFFFFF444 0x000000XX W
GP3SET 0xFFFFF454 0x000000XX W
GP4SET 0xFFFFF464 0x000000XX W
1
X = 0, 1, 2, or 3.
GPxSET are data set Port x registers.
Table 88. GPxSET MMR Bit Descriptions
Bit Description
31:24 Reserved.
23:16 Data Port x set bit. Set to 1 by user to set bit on Port x;
also sets the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0 Reserved.
Table 89. GPxCLR Registers
Name Address Default Value
1
Access
GP0CLR 0xFFFFF428 0x000000XX W
GP1CLR 0xFFFFF438 0x000000XX W
GP2CLR 0xFFFFF448 0x000000XX W
GP3CLR 0xFFFFF458 0x000000XX W
GP4CLR 0xFFFFF468 0x000000XX W
1
X = 0, 1, 2, or 3.
GPxCLR are data clear Port x registers.
Table 90. GPxCLR MMR Bit Descriptions
Bit Description
31:24 Reserved.
23:16 Data Port x clear bit. Set to 1 by user to clear bit on
Port x; also clears the corresponding bit in the GPxDAT
MMR. Cleared to 0 by user; does not affect the data out.
15:0 Reserved.
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I
2
Cs) and the programmable logic array
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 91.
Table 91. SPM Configuration
SPMMUX
GPIO UART UART/I
2
C/SPI PLA
(00) (01) (10) (11)
SPM0
P1.0
SIN
I2C0SCL
PLAI[0]
SPM1 P1.1 SOUT I2C0SDA PLAI[1]
SPM2 P1.2 RTS I2C1SCL PLAI[2]
SPM3 P1.3 CTS I2C1SDA PLAI[3]
SPM4 P1.4 RI SCLK PLAI[4]
SPM5 P1.5 DCD MISO PLAI[5]
SPM6 P1.6 DSR MOSI PLAI[6]
SPM7 P1.7 DTR
CS
PLAO[0]
SPM8 P0.7 ECLK/XCLK SIN PLAO[4]
SPM9 P2.0 CONV SOUT PLAO[5]
Table 91 also details the mode for each of the SPMMUX pins.
This configuration must be done via the GP0CON, GP1CON,
and GP2CON MMRs. By default, these 10 pins are configured
as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. It is fully compatible with the 16,450 serial
port standard. The UART performs serial-to-parallel conversions
on data characters received from a peripheral device or modem,
and parallel-to-serial conversions on data characters received
from the CPU. The UART includes a fractional divider for baud
rate generation and has a network addressable mode. The UART
function is made available on the 10 pins of the ADuC7019/20/
21/22/24/25/26/27/28/29 (see Table 92).
Table 92. UART Signal Description
Pin Signal Description
SPM0 (Mode 1) SIN Serial receive data.
SPM1 (Mode 1) SOUT Serial transmit data.
SPM2 (Mode 1) RTS Request to send.
SPM3 (Mode 1) CTS Clear to send.
SPM4 (Mode 1) RI Ring indicator.
SPM5 (Mode 1) DCD Data carrier detect.
SPM6 (Mode 1) DSR Data set ready.
SPM7 (Mode 1) DTR Data terminal ready.
SPM8 (Mode 2) SIN Serial receive data.
SPM9 (Mode 2) SOUT Serial transmit data.