Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 71 of 104
The serial communication adopts an asynchronous protocol,
which supports various word lengths, stop bits, and parity
generation options selectable in the configuration register.
Baud Rate Generation
There are two ways of generating the UART baud rate, normal
450 UART baud rate generation and the fractional divider.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the values
in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
DL×2×16-2
MHz78.41
=RateBaud
CD
Table 93 gives some common baud rate values.
Table 93. Baud Rate Using the Normal Baud Rate Generator
Baud Rate CD DL Actual Baud Rate % Error
9600 0 0x88 9600 0
19,200
0
0x44
19,200
0
115,200 0 0x0B 118,691 3
9600 3 0x11 9600 0
19,200 3 0x08 20,400 6.25
115,200 3 0x01 163,200 41.67
Fractional Divider
The fractional divider, combined with the normal baud rate
generator, produces a wider range of more accurate baud rates.
04955-032
/16DL UART
FBEN
CORE
CLOCK
/2
/(M+N/2048)
Figure 75. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as follows:






+×
×××
=
2048
2162
MHz78.41
N
MDL
Rate
Baud
CD
2×DL×16×2×RateBaud
MHz78.41
=
2048
N
+M
CD
For example, generation of 19,200 baud with CD bits = 3
(Table 93 gives DL = 0x08) is
2
8162
19200
MHz78
.41
2048
3
×
×××
=+
N
M
06
.1
2048
=+
N
M
where:
M = 1
N = 0.06 × 2048 = 128
2048
128
×2×8×16×2
MHz78.41
=RateBaud
3
where:
Baud Rate = 19,200 bps
Error = 0%, compared to 6.25% with the normal baud rate
generator.
UART Register Definitions
The UART interface consists of 12 registers: COMTX, COMRX,
COMDIV0, COMIEN0, COMDIV1, COMIID0, COMCON0,
COMCON1, COMSTA0, COMSTA1, COMSCR, and
COMDIV2.
Table 94. COMTX Register
Name Address Default Value Access
COMTX 0xFFFF0700 0x00 R/W
COMTX is an 8-bit transmit register.
Table 95. COMRX Register
Name Address Default Value Access
COMRX 0xFFFF0700 0x00 R
COMRX is an 8-bit receive register.
Table 96. COMDIV0 Register
Name Address Default Value Access
COMDIV0 0xFFFF0700 0x00 R/W
COMDIV0 is a low byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in the COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
Table 97. COMIEN0 Register
Name Address Default Value Access
COMIEN0 0xFFFF0704 0x00 R/W
COMIEN0 is the interrupt enable register.
Table 98. COMIEN0 MMR Bit Descriptions
Bit Name Description
7:4 N/A Reserved.
3 EDSSI Modem status interrupt enable bit. Set by
user to enable generation of an interrupt if
any of COMSTA1[3:1] is set. Cleared by user.
2 ELSI Rx status interrupt enable bit. Set by user to
enable generation of an interrupt if any of
COMSTA0[4:1] is set. Cleared by user.
1 ETBEI Enable transmit buffer empty interrupt. Set
by user to enable interrupt when buffer is
empty during a transmission. Cleared by user.
0 ERBFI Enable receive buffer full interrupt. Set by
user to enable interrupt when buffer is full
during a reception. Cleared by user.