Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 79 of 104
Table 140. I2CxDIV Registers
Name Address Default Value Access
I2C0DIV 0xFFFF0830 0x1F1F R/W
I2C1DIV 0xFFFF0930 0x1F1F R/W
I2CxDIV are the clock divider registers.
Table 141. I2CxIDx Registers
Name Address Default Value Access
I2C0ID0 0xFFFF0838 0x00 R/W
I2C0ID1 0xFFFF083C 0x00 R/W
I2C0ID2 0xFFFF0840 0x00 R/W
I2C0ID3 0xFFFF0844 0x00 R/W
I2C1ID0 0xFFFF0938 0x00 R/W
I2C1ID1 0xFFFF093C 0x00 R/W
I2C1ID2 0xFFFF0940 0x00 R/W
I2C1ID3
0xFFFF0944
0x00
R/W
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
Table 142. I2CxCCNT Registers
Name Address Default Value Access
I2C0CCNT 0xFFFF0848 0x01 R/W
I2C1CCNT 0xFFFF0948 0x01 R/W
I2CxCCNT are 8-bit start/stop generation counters. They hold
off SDA low for start and stop conditions.
Table 143. I2CxFSTA Registers
Name Address Default Value Access
I2C0FSTA 0xFFFF084C 0x0000 R/W
I2C1FSTA 0xFFFF094C 0x0000 R/W
I2CxFSTA are FIFO status registers.
Table 144. I2C0FSTA MMR Bit Descriptions
Bit
Access
Type Value Description
15:10 Reserved.
9 R/W Master transmit FIFO flush. Set by the
user to flush the master Tx FIFO.
Cleared automatically when the
master Tx FIFO is flushed. This bit
also flushes the slave receive FIFO.
8 R/W Slave transmit FIFO flush. Set by the
user to flush the slave Tx FIFO. Cleared
automatically after the slave Tx FIFO
is flushed.
7:6 R Master Rx FIFO status bits.
00 FIFO empty.
01 Byte written to FIFO.
10
One byte in FIFO.
11 FIFO full.
5:4 R Master Tx FIFO status bits.
00 FIFO empty.
01 Byte written to FIFO.
10
One byte in FIFO.
11 FIFO full.
3:2 R Slave Rx FIFO status bits.
00 FIFO empty.
01 Byte written to FIFO.
10 One byte in FIFO.
11 FIFO full.
1:0 R Slave Tx FIFO status bits.
00 FIFO empty.
01 Byte written to FIFO.
10 One byte in FIFO.
11 FIFO full.