Datasheet

Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 81 of 104
Table 148. PLACLK Register
Name Address Default Value Access
PLACLK 0xFFFF0B40 0x00 R/W
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. Note that the maximum frequency when using the
GPIO pins as the clock input for the PLA blocks is 44 MHz.
Table 149. PLACLK MMR Bit Descriptions
Bit Value Description
7 Reserved.
6:4 Block 1 clock source selection.
000 GPIO clock on P0.5.
001 GPIO clock on P0.0.
010 GPIO clock on P0.7.
011
HCLK.
100 OCLK (32.768 kHz) external crystal only.
101 Timer1 overflow.
Other Reserved.
3 Reserved.
2:0 Block 0 clock source selection.
000 GPIO clock on P0.5.
001 GPIO clock on P0.0.
010 GPIO clock on P0.7.
011 HCLK.
100 OCLK (32.768 kHz) external crystal only.
101 Timer1 overflow.
Other Reserved.
Table 150. PLAIRQ Register
Name Address Default Value Access
PLAIRQ 0xFFFF0B44 0x00000000 R/W
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the IRQ.
Table 151. PLAIRQ MMR Bit Descriptions
Bit Value Description
15:13 Reserved.
12 PLA IRQ1 enable bit. Set by user to enable
IRQ1 output from PLA. Cleared by user to
disable IRQ1 output from PLA.
11:8 PLA IRQ1 source.
0000 PLA Element 0.
0001 PLA Element 1.
1111 PLA Element 15.
7:5 Reserved.
4 PLA IRQ0 enable bit. Set by user to enable
IRQ0 output from PLA. Cleared by user to
disable IRQ0 output from PLA.
3:0 PLA IRQ0 source.
0000 PLA Element 0.
0001 PLA Element 1.
1111 PLA Element 15.
Table 152. Feedback Configuration
Bit Value PLAELM0 PLAELM1 to PLAELM7 PLAELM8 PLAELM9 to PLAELM15
10:9 00 Element 15 Element 0 Element 7 Element 8
01 Element 2 Element 2 Element 10 Element 10
10 Element 4 Element 4 Element 12 Element 12
11 Element 6 Element 6 Element 14 Element 14
8:7 00 Element 1 Element 1 Element 9 Element 9
01 Element 3 Element 3 Element 11 Element 11
10 Element 5 Element 5 Element 13 Element 13
11 Element 7 Element 7 Element 15 Element 15