Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 16/32-Bit 41.78 MHz I/O number 40

Precision Analog Microcontroller, 12-Bit Analog I/O, Large

Memory, ARM7TDMI MCU with Enhanced IRQ Handler

Data Sheet

ADuC7124/ADuC7126

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

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FEATURES

Analog input/output

Multichannel, 12-bit, 1 MSPS ADC

Up to 16 ADC channels

Fully differential and single-ended modes

0 V to V

REF

analog input range

12-bit voltage output DACs

4 DAC outputs available

On-chip voltage reference

On-chip temperature sensor (±3°C)

Voltage comparator

Microcontroller

ARM7TDMI core, 16-bit/32-bit RISC architecture

JTAG port supports code download and debug

Clocking options

Trimmed on-chip oscillator (±3%)

External watch crystal

External clock source up to 41.78 MHz

41.78 MHz PLL with programmable divider

Memory

126 kB Flash/EE memory, 32 kB SRAM

In-circuit download, JTAG-based debug

Software-triggered in-circuit reprogrammability

Vectored interrupt controller for FIQ and IRQ

8 priority levels for each interrupt type

Interrupt on edge or level external pin inputs

On-chip peripherals

2× fully I

C-compatible channels

SPI (20 MBPS in master mode, 10 MBPS in slave mode)

With 4-byte FIFO on input and output stages

2× UART channels

With 16-byte FIFO on input and output stages

Up to 40 GPIO port

All GPIOs are 5 V tolerant

4× general-purpose timers

Watchdog timer (WDT) and wake-up timer

Programmable logic array (PLA)

16 PLA elements

16-bit, 6-channel PWM

Power supply monitor

Power

Specified for 3 V operation

Active mode: 11.6 mA at 5 MHz, 33.3 mA at 41.78 MHz

Packages and temperature range

Fully specified for −40°C to +125°C operation

64-lead LFCSP and 80-lead LQFP

Tools

Low cost QuickStart development system

Full third-party support

APPLICATIONS

Industrial control and automation systems

Smart sensors, precision instrumentation

Base station systems, optical networking

Patient monitoring

FUNCTIONAL BLOCK DIAGRAM

1MSPS

12-BIT ADC

DAC0

DAC1

DAC2

DAC3

PWM

EXTERNAL

MEMORY

INTERFACE

ADuC7124/ADuC7126

ADC0

XCLKI

XCLKO

RST

REF

ADC15

MUX

TEMP

SENSOR

BAND GAP

REF

OSC

AND PLL

PSM

POR

CMP0

CMP1

CMP

OUT

PLA

VECTORED

INTERRUPT

CONTROLLER

4 GENERAL-

PURPOSE TIMERS

8k × 32 SRAM

63k × 16 FLASH/EEPROM

SPI, 2 × I

2 × UART

GPIO

JTAG

ARM7TDMI-BASED MCU WITH

ADDITIONAL PERIPHERALS

09123-001

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

Figure 1.

Summary of content (108 pages)

PAGE 1
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler ADuC7124/ADuC7126 Data Sheet FEATURES On-chip peripherals 2× fully I2C-compatible channels SPI (20 MBPS in master mode, 10 MBPS in slave mode) With 4-byte FIFO on input and output stages 2× UART channels With 16-byte FIFO on input and output stages Up to 40 GPIO port All GPIOs are 5 V tolerant 4× general-purpose timers Watchdog timer (WDT) and wake-up timer Programmable logic array (PLA) 16 PLA eleme
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ADuC7124/ADuC7126 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Band Gap Reference................................................................... 43 Applications....................................................................................... 1 Nonvolatile Flash/EE Memory ..................................................... 44 Functional Block Diagram ....................................................
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Data Sheet ADuC7124/ADuC7126 REVISION HISTORY 5/12—Rev. B to Rev. C Changed bit to byte in General Description Section....................4 Changes to Table 2 and Table 3 .......................................................8 Changes to Table 4 and to Figure 2 and Figure 3 ..........................9 Changes to Table 5 and Figure 4....................................................10 Changes to Table 6 and Figure 5....................................................11 Changes Table 7 and Figure 6 .....
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ADuC7124/ADuC7126 Data Sheet GENERAL DESCRIPTION The ADuC7124/ADuC7126 are fully integrated, 1 MSPS, 12-bit data acquisition system incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins. The ADC can operate in single-ended or differential input mode. The ADC input voltage range is 0 V to VREF.
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Data Sheet ADuC7124/ADuC7126 SPECIFICATIONS AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity Min Max 5 ±0.6 ±1.0 ±0.5 +0.7/−0.
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ADuC7124/ADuC7126 Parameter ANALOG OUTPUTS Output Voltage Range 0 Output Voltage Range 1 Output Voltage Range 2 Output Impedance Data Sheet Unit Test Conditions/Comments 0 to DACREF 0 to 2.5 0 to DACVDD 0.5 V V V Ω DACREF range: DACGND to DACVDD DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage Input Offset Voltage Drift Input Offset Current Input Bias Current Gain Unity Gain Frequency CMRR Settling Time Output Slew Rate PSRR ±0.4 4 2 2.5 70 4.5 78 12 3.
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Data Sheet Parameter LOGIC INPUTS3 VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage 11 CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance INTERNAL OSCILLATOR MCU CLOCK RATE4 From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock ADuC7124/ADuC7126 Min IOVDD Current in Pause Mode IOVDD Current in Sleep Mode Additio
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ADuC7124/ADuC7126 Parameter ESD TESTS HBM Passed Up To FICDM Passed Up To Data Sheet Min Typ Max Unit 3 1.5 kV kV Test Conditions/Comments 2.5 V reference, TA = 25°C 1 All ADC channel specifications are guaranteed during normal core operation. Apply to all ADC input channels. Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release.
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Data Sheet ADuC7124/ADuC7126 tBUF tR MSB tDSU LSB tSHD P tF tDHD 2–7 8 9 1 tL S tR tRSU tH 1 SCL (I) MSB tDSU tDHD tPSU ACK S(R) REPEATED START STOP START CONDITION CONDITION tF 09123-029 SDA (I/O) Figure 2. I2C-Compatible Interface Timing SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tUCLK = 23.9 ns.
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ADuC7124/ADuC7126 Data Sheet Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max Unit ns ns ns ns ns ns ns ns ns ns 25 75 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
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Data Sheet ADuC7124/ADuC7126 Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter tCS Description CS to SCLK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge 1 Data input hold time after SCLK edge1 Data output fall time Data output rise time SCLK rise time SCLK fall time CS high after SCLK edge Typ Max (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.
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ADuC7124/ADuC7126 Data Sheet Table 7.
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Data Sheet ADuC7124/ADuC7126 ABSOLUTE MAXIMUM RATINGS AGND = GNDREF = DACGND = GNDREF, TA = 25°C, unless otherwise noted. Table 8.
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ADuC7124/ADuC7126 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 GNDREF AGND AVDD DACREF VREF RTCK P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] P1.2/SPM2/RTS/I2C1SCL/PLAI[2] PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADCNEG DACGND DACV DD DAC0/ADC12 DAC1/ADC13 TMS TDI XCLKO XCLKI BM/P0.
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Data Sheet Pin No. 14 15 Mnemonic XCLKO XCLKI 16 BM/P0.0/CMPOUT/PLAI[7] 17 18 DGND LVDD 19 20 21 IOVDD IOGND P4.6/PLAO[14] 22 P4.7/PLAO[15] 23 P0.6/T1/MRST/PLAO[3] 24 25 26 TCK TDO P3.0/PWM0/PLAI[8] 27 P3.1/PWM1/PLAI[9] 28 P3.2/PWM2/PLAI[10] 29 P3.3/PWM3/PLAI[11] 30 P0.3/TRST/ADCBUSY 31 P3.4/PWM4/PLAI[12] 32 P3.5/PWM5/PLAI[13] 33 34 RST IRQ0/P0.4/PWMTRIP/PLAO[1] ADuC7124/ADuC7126 Description Output from the Crystal Oscillator Inverter.
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ADuC7124/ADuC7126 Pin No. 35 Mnemonic IRQ1/P0.5/ADCBUSY/PLAO[2] 36 P2.0/SPM9/PLAO[5]/CONVSTART/SOUT0 37 P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 38 39 40 IOGND IOVDD P3.6/PWMTRIP/PLAI[14] 41 P3.7/PWMSYNC/PLAI[15] 42 P1.7/SPM7/DTR/SPICS/PLAO[0] 43 P1.6/SPM6/PLAI[6] 44 P4.0/PLAO[8]/SIN1 45 P4.1/PLAO[9]/SOUT1 46 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 47 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 48 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] 49 P1.2/SPM2/RTS/I2C1SCL/PLAI[2] Data Sheet Description Multifunction I/O Pin.
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Data Sheet Pin No. 50 Mnemonic P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] 51 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] 52 P4.2/PLAO[10] 53 P4.3/PLAO[11] 54 P4.4/PLAO[12] 55 56 RTCK VREF 57 58 59 60 DACREF AVDD AGND GNDREF 61 62 63 ADC0 ADC1 ADC2/CMP0 64 ADC3/CMP1 ADuC7124/ADuC7126 Description General-Purpose Input and Output Port 1.1 (P1.1). Serial Port Multiplexed (SPM1). UART download pin, UART0 Output (SOUT0). I2C0 (I2C0SDA). Programmable Logic Array Input Element 1 (PLAI[1]).
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P1.2/SPM2/RTS/I2C1SCL/PLAI[2] P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13]/RTCK IOVDD IOGND VREF DACREF AVDD AGND AGND GNDREF ADC11 ADC0 ADC1 ADC2/CMP0 Data Sheet ADC3/CMP1 ADuC7124/ADuC7126 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] 59 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 3 58 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 ADC7 4 57 P4.
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Data Sheet Pin No. 11 Mnemonic DAC0/ADC12 12 DAC1/ADC13 13 DAC2/ADC14 14 DAC3/ADC15 15 16 17 TMS TDI P0.1/PWM4/BLE 18 19 XCLKO XCLKI 20 BM/P0.0/CMPOUT/PLAI[7]/MS0 21 22 DGND LVDD 23 24 25 IOVDD IOGND P4.6/AD14/PLAO[14] 26 P4.7/AD15/PLAO[15] 27 P0.6/T1/MRST/PLAO[3]/MS3 28 29 30 TCK TDO P0.2/PWM5/BHE 31 P3.0/AD0/PWM0/PLAI[8] 32 P3.1/AD1/PWM1/PLAI[9] 33 P3.2/AD2/PWM2/PLAI[10] ADuC7124/ADuC7126 Description DAC0 Voltage Output (DAC0).
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ADuC7124/ADuC7126 Pin No. 34 Mnemonic P3.3/AD3/PWM3/PLAI[11] 35 P2.4/SPM13/PWM0/MS0/SOUT1 36 P0.3/TRST/A16/ADCBUSY 37 P2.5/PWM1/MS1 38 P2.6/PWM2/MS2 39 P3.4/AD4/PWM4/PLAI[12] 40 P3.5/AD5/PWM5/PLAI[13] 41 42 RST IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 43 IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2 44 P2.7/PWM3/MS3 45 P2.0/SPM9/PLAO[5]/CONVSTART/SOUT0 46 P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0 47 48 IOGND IOVDD Data Sheet Description General-Purpose Input and Output Port 3.3 (P3.3).
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Data Sheet Pin No. 49 Mnemonic P2.3/SPM12/AE/SIN1 50 P2.1/WS/PWM0/PLAO[6] 51 P2.2/RS/PWM1/PLAO[7] 52 P3.6/AD6/PWMTRIP/PLAI[14] 53 P3.7/AD7/PWMSYNC/PLAI[15] 54 P1.7/SPM7/DTR/SPICS/PLAO[0] 55 P1.6/SPM6/PLAI[6] 56 P4.0/SPM10/SIN1/AD8/PLAO[8] 57 P4.1/SPM11/SOUT1/AD9/PLAO[9] 58 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 59 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 60 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] 61 P1.2/SPM2/RTS/I2C1SCL/PLAI[2] ADuC7124/ADuC7126 Description General-Purpose Input and Output Port 2.
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ADuC7124/ADuC7126 Pin No. 62 Mnemonic P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] 63 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] 64 P4.2/AD10/PLAO[10] 65 P4.3/AD11/PLAO[11] 66 P4.4/AD12/PLAO[12] 67 P4.5/AD13/PLAO[13]/RTCK 68 69 70 IOVDD IOGND VREF 71 72 73, 74 75 DACREF AVDD AGND GNDREF 76 77 78 79 ADC11 ADC0 ADC1 ADC2/CMP0 80 ADC3/CMP1 Data Sheet Description General-Purpose Input and Output Port 1.1 (P1.1). Serial Port Multiplexed (SPM1). UART0 Output (SOUT0). I2C0 (I2C0SDA).
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Data Sheet ADuC7124/ADuC7126 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.3 0.3 0.2 DNL (LSB) 0.1 0 0.1 0 –0.1 09123-208 –0.1 ADC CODES 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 –0.3 –0.4 –0.4 –0.5 ADC CODES 3500 3000 2500 2000 –0.6 1500 4000 4095 3500 3000 2500 2000 1500 –0.6 0 –0.5 4000 4095 09123-211 –0.2 –0.3 09123-209 –0.2 1000 3500 0 –0.1 1000 –0.1 500 0 4000 4095 INL (LSB) 0.6 0.5 500 3000 Figure 11.
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Data Sheet 0.4 0.4 0.3 0.3 0.2 0.2 DNL (LSB) 0.1 0 –0.1 0.1 0 09123-212 ADC CODES 4000 4095 3500 3000 2500 ADC CODES Figure 13. Typical DNL Error, Temperature 25°C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz Worst-Case Positive = 0.42 LSB, Code 3583 Worst-Case Negative = −0.32 LSB, Code 3073 Figure 15. Typical DNL Error, Temperature 25°C, VREF = Internal 2.
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Data Sheet ADuC7124/ADuC7126 –20 –40 –60 –80 –100 –120 –140 0 50 100 150 –20 –40 –60 –80 –100 –120 –140 174.1 SNR: 65.97dB THD: –78.63dB PHSN: –77.83dB, 146.6038kHz 0 09123-219 0 SINAD, THD, AND PHSN OF ADC (dB) 20 SNR: 69.85dB THD: –79.91dB PHSN: –82.93dB, 29.771kHz 09123-216 0 50 100 FREQUENCY (kHz) 174.1 Figure 20. SINAD, THD, and PHSN of ADC, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC15/DAC3, ADCCN = ADC0 Figure 17. SINAD, THD, and PHSN of ADC, VREF = Internal 2.
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ADuC7124/ADuC7126 Data Sheet TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
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Data Sheet ADuC7124/ADuC7126 OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with four additional features. T support for the Thumb® (16-bit) instruction set. D support for debug. M support for long multiplications.
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ADuC7124/ADuC7126 Data Sheet More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in the following materials from ARM: • • DDI0029G, ARM7TDMI Technical Reference Manual DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a fast interrupt request (FIQ) consists of the following: • • • • The longest time the request can take to pass through the synchronizer The time for the longest instruction to complete (the longe
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Data Sheet ADuC7124/ADuC7126 MEMORY ORGANIZATION The ADuC7124/ADuC7126 incorporate three separate blocks of memory: 32 kB of SRAM and two 64 kB blocks of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the system kernel. These blocks are mapped as shown in Figure 24. FLASH/EE MEMORY Note that, by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000.
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ADuC7124/ADuC7126 Data Sheet 0xFFFFFFFF 0xFFFFF880 0xFFFFF800 FLASH CONTROL INTERFACE 1 FLASH CONTROL INTERFACE 0 GPIO 0xFFFFF400 0xFFFFF000 EXTERNAL MEMORY PWM 0xFFFF0F80 PLA 0xFFFF0B00 SPI 0xFFFF0A00 I2C1 0xFFFF0900 I2C0 0xFFFF0800 UART1 0xFFFF0740 UART0 0xFFFF0700 DAC 0xFFFF0600 ADC 0xFFFF0500 0xFFFF048C 0xFFFF0440 0xFFFF0404 0xFFFF0360 0xFFFF0340 0xFFFF0320 BAND GAP REFERENCE POWER SUPPLY MONITOR PLL AND OSCILLATOR CONTROL WATCHDOG TIMER WAKE-UP TIMER GENERAL-PURPOSE TIMER T
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Data Sheet ADuC7124/ADuC7126 Table 11.
PAGE 32
ADuC7124/ADuC7126 Data Sheet Table 14. PLL/PSM Base Address = 0xFFFF0400 Address 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF0434 0xFFFF0438 0xFFFF043C Name POWKEY1 POWCON0 POWKEY2 PLLKEY1 PLLCON PLLKEY2 POWKEY3 POWCON1 POWKEY4 Byte 2 1 2 4 1 4 2 2 2 Access Type W R/W W W R/W W W R/W W Table 15.
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Data Sheet ADuC7124/ADuC7126 Table 19.
PAGE 34
ADuC7124/ADuC7126 Data Sheet Table 22.
PAGE 35
Data Sheet ADuC7124/ADuC7126 Table 25.
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ADuC7124/ADuC7126 Data Sheet Table 27.
PAGE 37
Data Sheet ADuC7124/ADuC7126 ADC CIRCUIT OVERVIEW Fully differential mode, for small and balanced signals Single-ended mode, for any single-ended signals Pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input 1111 1111 1110 1111 1111 1101 1111 1111 1100 1LSB = FULLSCALE 4096 0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0V 1LSB +FS – 1LSB VOLTAGE INPUT AVDD VCM VCM 2VREF VCM 2VREF 0 09123-011
PAGE 38
ADuC7124/ADuC7126 Data Sheet TYPICAL OPERATION MMRS INTERFACE Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The ADC is controlled and configured via the eight MMRs. ADCCON Register The top four bits are the sign bits. The 12-bit result is placed in Bit 16 to Bit 27 as shown in Figure 30.
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Data Sheet Bit [2:0] Value 000 001 010 011 100 101 Other ADuC7124/ADuC7126 Description Conversion type. Enable CONVSTART pin as a conversion input. Enable Timer1 as a conversion input. Enable Timer0 as a conversion input. Single software conversion. Sets to 000 after conversion (note that Bit 7 of ADCCON MMR should be cleared after starting a single software conversion to avoid further conversions triggered by the CONVSTART pin). Continuous software conversion. PLA conversion. Reserved.
PAGE 40
ADuC7124/ADuC7126 Data Sheet Position A. The comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register.
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Data Sheet ADuC7124/ADuC7126 Single-Ended Mode For ac applications, removing high frequency components from the analog input signal is recommended by using an RC lowpass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier.
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ADuC7124/ADuC7126 Data Sheet CALIBRATION By default, the factory-set values written to the ADC offset (ADCOF) and gain coefficient registers (ADCGN) yield optimum performance in terms of end-point errors and linearity for standalone operation of the part (see the Specifications section).
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Data Sheet ADuC7124/ADuC7126 response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system. An external buffer is required because of the low drive capability of the VREF output (<5 μA). A programmable option also allows an external reference input on the VREF pin. Note that it is not possible to disable the internal reference.
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ADuC7124/ADuC7126 Data Sheet NONVOLATILE FLASH/EE MEMORY The ADuC7124/ADuC7126 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, incircuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, flash memory is often and more correctly referred to as Flash/EE memory.
PAGE 45
Data Sheet ADuC7124/ADuC7126 for serial downloading via the I2C. A USB-to-I2C download dongle can be purchased from Analog Devices, Inc. This board connects to the USB port of a PC and to the I2C port of the ADuC7126. The part number is USB-I2C/LIN-CONV-Z. value 0xDEAD, the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. The AN-806 Application Note describes the protocol for serial downloading via the I2C in more detail.
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ADuC7124/ADuC7126 Data Sheet Table 45. FEE1STA Register Name FEE1STA Address 0xFFFFF880 Table 50. FEE1SGN Register Default Value 0x0000 Access R Default Value 0x80 Access R/W Address 0xFFFFF884 Table 47. FEE1CON Register Name FEE1CON Address 0xFFFFF888 Default Value 0x00 Access R/W Table 48. FEE1DAT Register Name FEE1DAT Address 0xFFFFF88C Access R/W Access R Table 51.
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Data Sheet ADuC7124/ADuC7126 Table 54. FEExMOD MMR Bit Descriptions Bit [7:5] 4 3 2 [1:0] Description Reserved. Flash/EE interrupt enable. Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by the user to disable the Flash/EE interrupt. Erase/write command protection. Set by the user to enable the erase and write commands. Cleared to protect the Flash/EE memory against the erase/write command. Reserved. Should always be set to 0 by the user.
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ADuC7124/ADuC7126 Data Sheet Table 56. FEE0PRO and FEE0HID MMR Bit Descriptions Bit 31 [30:0] Description Read protection. Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. Write protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 0 to Page 3. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages. Table 57. FEE1PRO and FEE1HID MMR Bit Descriptions Bit 31 30 [29:0] Description Read protection.
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Data Sheet ADuC7124/ADuC7126 Table 60. RSTSTA MMR Bit Descriptions Table 59. REMAP MMR Bit Descriptions (Address = 0xFFFF0220. Default Value = 0x00) Bit 0 Name Remap Description Remap bit. Set by the user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to Address 0x00000000. Bit [7:3] 2 Description Reserved. Software reset. Set by the user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Watchdog timeout.
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ADuC7124/ADuC7126 Data Sheet RSTKEY0 Register RSTKEY1 Register Name: RSTKEY0 Name: RSTKEY1 Address: 0xFFFF0248 Address: 0xFFFF0250 Default Value: N/A Default Value: N/A Access Write only Access: Write only Rev.
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Data Sheet ADuC7124/ADuC7126 OTHER ANALOG PERIPHERALS DAC Table 65. DAC0DAT MMR Bit Descriptions The ADuC7124/ADuC7126 incorporate two, or four, 12-bit voltage output DACs on chip, depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Bit [31:28] [27:16] [15:0] Each DAC has three selectable ranges: 0 V to VREF (internal band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD. DACREF is equivalent to an external reference for the DAC.
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ADuC7124/ADuC7126 Data Sheet Configuring DAC Buffers in Op Amp Mode AVDD In op amp mode, the DAC output buffers are used as an op amp with the DAC itself disabled. AVDD – 100mV If DACBCFG Bit 0 is set, ADC0 is the positive input to the op amp, ADC1 is the negative input, and DAC0 is the output. In this mode, the DAC should be powered down by clearing Bit 0 and Bit 1 of DAC0CON. If DACBCFG Bit 1 is set, ADC2 is the positive input to the op amp, ADC3 is the negative input, and DAC1 is the output.
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Data Sheet ADuC7124/ADuC7126 DACBKEY1 Register Name: DACBKEY1 Address: 0xFFFF0650 Default Value: 0x0000 Access: Write Table 68. PSMCON MMR Bit Descriptions Bit 3 Name CMP DACBKEY2 Register Description Comparator bit. This is a read-only bit that directly reflects the state of the comparator. Read 1 indicates that the IOVDD supply is above its selected trip point or that the PSM is in power-down mode. Read 0 indicates that the IOVDD supply is below its selected trip point.
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ADuC7124/ADuC7126 Data Sheet The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 69. Bit 1 Value Name CMPORI Description Comparator output rising edge interrupt. Set automatically when a rising edge occurs on the monitored voltage (CMP0). Cleared by user by writing a 1 to this bit. Comparator output falling edge interrupt. Set automatically when a falling edge occurs on the monitored voltage (CMP0). Cleared by user.
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Data Sheet ADuC7124/ADuC7126 External Crystal Selection External Clock Selection To switch to an external crystal, the user must follow this procedure: To switch to an external clock on P0.7, configure P0.7 in Mode 1. The external clock can be up to 41.78 MHz, providing the tolerance is 1%. 1. Enable the Timer2 interrupt and configure it for a timeout period of >120 μs. 2. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit. 3.
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ADuC7124/ADuC7126 Data Sheet MMRs and Keys POWCON0 Register The operating mode, clocking mode, and programmable clock divider are controlled via three MMRs, PLLCON (see Table 73), and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and the power-down mode, and POWCON1 controls the clock frequency to I2C and SPI. Name: POWCON0 Address: 0xFFFF0408 Default Value: 0x0003 Access: Read/write Table 72. PLLKEYx Registers Table 75.
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Data Sheet ADuC7124/ADuC7126 Table 77. POWCON1 MMR Bit Descriptions 1 The POWCON1 write sequence is as follows: Bit [15:12] 11 Value Name 1 PWMPO 1. 2. 3. [10:9] 8 00 PWMCLKDIV SPIPO [7:6] SPICLKDIV 00 01 10 11 5 I2C1PO [4:3] I2C1CLKDIV 00 01 10 11 2 I2C0PO [1:0] I2C0CLKDIV 00 01 10 11 Description Reserved. Clearing this bit powers down the PWM. Always clear to 00. Clearing this bit powers down the SPI. SPI block driving clock divider bits. 41.78 MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz.
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ADuC7124/ADuC7126 Data Sheet DIGITAL PERIPHERAL GENERAL-PURPOSE INPUT/OUTPUT Table 78. GPIO Pin Function Descriptions The ADuC7124/ADuC7126 provide 40 general-purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning the GPIOs support an input voltage of 5 V. Port 0 In general, many of the GPIO pins have multiple functions (see the Pin Configurations and Function Descriptions section for pin function definitions). By default, the GPIO pins are configured in GPIO mode.
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Data Sheet ADuC7124/ADuC7126 Table 79. GPxCON Registers Access R/W R/W R/W R/W R/W GPxCON are the Port x control registers that select the function of each pin of Port x, as described in Table 80. Table 80. GPxCON MMR Bit Descriptions Bit [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] Description Reserved. Select function of Px.7 pin. Reserved. Select function of Px.6 pin. Reserved. Select function of Px.5 pin. Reserved.
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ADuC7124/ADuC7126 Data Sheet The drive strength bits can be written only once after reset. Additional writing to related bits has no effect on drive strength. The GPIO drive strength and pull-up disable are not always adjustable for GPIO port. Some control bits cannot be changed. See Table 78 for details. Table 89. GPxCLR MMR Bit Descriptions Bit [31:24] [23:16] Table 84.
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Data Sheet ADuC7124/ADuC7126 Baud Rate Generation Error is 0%, compared to 6.25% with the normal baud rate generator. There are two ways of generating the UART baud rate, using normal 450 UART baud rate generation and using the fractional divider. UART Register Definitions COM0TX Register Normal 450 UART Baud Rate Generation Name: COM0TX The baud rate is a divided version of the core clock using the value in the COMxDIV0 and COMxDIV1 MMRs (16-bit value, DL).
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ADuC7124/ADuC7126 Data Sheet COM1DIV0 Register COM0DIV1 Register Name: COM1DIV0 Name: COM0DIV1 Address: 0xFFFF0740 Address: 0xFFFF0704 Default Value: 0x00 Default Value: 0x00 Access: Read/write Access: Read/write COM1DIV0 is a low byte divisor latch for UART1. COM1TX, COM1RX, and COM1DIV0 share the same address location. COM1TX and COM1RX can be accessed when Bit 7 in COM1CON0 register is cleared. COM1DIV0 can be accessed when Bit 7 of COM1CON0 is set.
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Data Sheet ADuC7124/ADuC7126 Table 93. COMxIID0 MMR Bit Descriptions COM1FCR Register Bit [7:6] Name: COM1FCR Address: 0xFFFF0748 Default Value: 0x00 Access: Read/write [5:4] [3:1] 0 1 Name FIFOMODE Reserved STATUS[2:0] NINT Description FIFO mode flag. 0x0: non-FIFO mode. 0x1: reserved. 0x2: reserved. 0x3: FIFO mode. Set automatically if FIFOEN is set. Interrupt status bits that work only when NINT is set. [000]: modem status interrupt. Cleared by reading COMxSTA1. Priority 4.
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ADuC7124/ADuC7126 Data Sheet COM1CON1 Register COM1CON0 Register Name: COM1CON0 Name: COM1CON1 Address: 0xFFFF074C Address: 0xFFFF0750 Default Value: 0x00 Default Value: 0x00 Access: Read/write Access: Read/write COM1CON0 is the line control register for UART1. COM1CON1 is the modem control register for UART1. Table 95. COMxCON0 MMR Bit Descriptions Table 96.
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Data Sheet ADuC7124/ADuC7126 COM1STA0 Register Name: COM1STA0 Address: 0xFFFF0754 Default Value: 0xE0 Access: Read only Bit 1 Name OE 0 DR Description Overrun error. For non-FIFO mode, set automatically if data is overwritten before being read. Cleared automatically. For FIFO mode, set automatically if an overrun error has been detected. An overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register.
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ADuC7124/ADuC7126 Data Sheet COM0DIV2 Register MOSI (Master Out, Slave In) Pin Name: COM0DIV2 Address: 0xFFFF072C Default Value: 0x0000 Access: Read/write The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first.
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Data Sheet ADuC7124/ADuC7126 SPI Registers The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x0000 Access: Read only Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes. Table 100.
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ADuC7124/ADuC7126 Data Sheet SPIDIV Register SPIRX Register Name: SPIRX Name: SPIDIV Address: 0xFFFF0A04 Address: 0xFFFF0A0C Default Value: 0x00 Default Value: 0x00 Access: Read only Access: Read/write Function: This 8-bit MMR is the SPI receive register. Function: This 8-bit MMR is the SPI baud rate selection register. SPITX Register SPICON Register Name: SPITX Address: 0xFFFF0A08 Default Value: 0x00 Access: Write only Function: This 8-bit MMR is the SPI transmit register.
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Data Sheet Bit 9 Name SPIOEN 8 SPIROW 7 SPIZEN 6 SPITMDE 5 SPILF 4 SPIWOM 3 SPICPO 2 SPICPH 1 SPIMEN 0 SPIEN ADuC7124/ADuC7126 Description Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is cleared. SPIRX overflow overwrite enable. Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received.
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ADuC7124/ADuC7126 Data Sheet I2C Configuring External Pins for I2C Functionality The ADuC7124/ADuC7126 incorporate two I2C peripherals that can be configured as a fully I2C-compatible I2C bus master device or as a fully I2C bus compatible slave device. Both I2C channels are identical. Therefore, the following descriptions apply to both channels. The I2C pins of the ADuC7124/ADuC7126 device are P1.0 and P1.1 for I2C0 and P1.2 and P1.3 for I2C1.
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Data Sheet ADuC7124/ADuC7126 Master Mode In master mode, the I2CxADR0 register is programmed with the I2C address of the device. I2C Master Registers I2C Master Control Register Name: I2C0MCON, I2C1MCON Address: 0xFFFF0800, 0xFFFF0900 0x0000, 0x0000 I2CxADR0[7:3] must be set to 11110b. Default Value: I2CxADR0[2:1] = Address Bits[9:8]. Access: Read/write I2CxADR1[7:0] = Address Bits[7:0]. Function: This 16-bit MMR configures the I2C peripheral in master mode.
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ADuC7124/ADuC7126 Data Sheet I2C Master Status Register Name: I2C0MSTA, I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I2C status register in master mode. Table 103. I2CxMSTA MMR Bit Descriptions Bit [15:11] 10 Name 9 I2CMRxFO 8 I2CMTC 7 I2CMNA 6 I2CMBUSY 5 I2CAL 4 I2CMNA 3 I2CMRXQ 2 I2CMTXQ [1:0] I2CMTFSTA I2CBBUSY Description Reserved. I2C bus busy status bit.
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Data Sheet ADuC7124/ADuC7126 I2C Master Receive Register I2C Master Current Read Count Register Name: I2C0MRX, I2C1MRX Name: I2C0MCNT1, I2C1MCNT1 Address: 0xFFFF0808, 0xFFFF0908 Address: 0xFFFF0814, 0xFFFF0914 Default Value: 0x00 Default Value: 0x00, 0x00 Access: Read only Access: Read only Function: This 8-bit MMR is the I2C master receive register. Function: This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device.
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ADuC7124/ADuC7126 Data Sheet I2C Address 1 Register Table 108. I2CxDIV MMR Name: I2C0ADR1, I2C1ADR1 Bit [15:8] Name DIVH Address: 0xFFFF081C, 0xFFFF091C Default Value: 0x00 [7:0] DIVL Access: Read/write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. Description These bits control the duration of the high period of SCL. These bits control the duration of the low period of SCL.
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Data Sheet ADuC7124/ADuC7126 Bit 5 Name I2CSETEN 4 I2CGCCLR 3 I2CHGCEN 2 I2CGCEN 1 ADR10EN 0 I2CSEN Description I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit transmission. I2C general call status and ID clear bit.
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ADuC7124/ADuC7126 Bit [12:11] Name I2CID[1:0] 10 I2CSS [9:8] I2CGCID[1:0] 7 I2CGC 6 I2CSBUSY 5 I2CSNA 4 I2CSRxFO 3 I2CSRXQ 2 I2CSTXQ 1 I2CSTFE 0 I2CETSTA Data Sheet Description I2C address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. [11] = received address matches I2CxID3. I2C stop condition after start detected bit.
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Data Sheet ADuC7124/ADuC7126 I2C Common Registers I2C FIFO Status Register I2C Slave Receive Registers Name: I2C0SRX, I2C1SRX Address: 0xFFFF0830, 0xFFFF0930 Default Value: 0x00 Access: Read Function: This 8-bit MMR is the I2C slave receive register. I2C Slave Transmit Registers Name: I2C0STX, I2C1STX Address: 0xFFFF0834, 0xFFFF0934 Default Value: 0x00 Access: Write Function: This 8-bit MMR is the I2C slave transmit register.
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ADuC7124/ADuC7126 Data Sheet PWM GENERAL OVERVIEW The ADuC7124/ADuC7126 integrate a 6-channel PWM interface (PWM0 to PWM5). The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins.
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Data Sheet ADuC7124/ADuC7126 Table 113. PWMCON0 MMR Bit Descriptions Bit 14 Name SYNC 13 PWM5INV 12 PWM3INV 11 PWM1INV 10 PWMTRIP 9 ENA [8:6] PWMCP[2:0] 5 POINV 4 HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN 1 Description Enables PWM synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P3.7/PWMSYNC pin. Cleared by the user to ignore transitions on the P3.7/PWMSYNC pin.
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ADuC7124/ADuC7126 Data Sheet Table 114. PWM Output Selection, HMODE = 1 1 2 DIR X X 0 1 0 1 PWM0 1 1 0 HS HS 1 PWM Outputs2 PWM1 PWM2 1 1 0 1 0 HS LS 0 LS 1 1 HS PWM3 1 0 LS 0 1 LS Table 116. PWMCON1 MMR Bit Descriptions (Address = 0xFFFF0FB4; Default Value = 0x00) Bit 7 Value [3:0] CSD3 X = don’t care. HS = high side, LS = low side. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 115.
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Data Sheet ADuC7124/ADuC7126 PROGRAMMABLE LOGIC ARRAY (PLA) Every ADuC7124/ADuC7126 integrates a fully programmable logic array (PLA) that consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA element contains a two-input look up table that can be configured to generate any logic output function based on two inputs and a flip-flop. This is represented in Figure 51.
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ADuC7124/ADuC7126 Data Sheet PLACLK Register PLAIRQ Register Name: PLACLK Name: PLAIRQ Address: 0xFFFF0B40 Address: 0xFFFF0B44 Default Value: 0x00 Default Value: 0x00000000 Access: Read/write Access: Read/write PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ. Table 120.
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Data Sheet ADuC7124/ADuC7126 PLAADC Register Table 124. PLADIN MMR Bit Descriptions Name: PLAADC Address: 0xFFFF0B48 Default Value: 0x00000000 PLADOUT Register Access: Read/write Name: PLADOUT PLAADC is the PLA source for the ADC start conversion signal. Address: 0xFFFF0B50 Table 123. PLAADC MMR Bit Descriptions Default Value: 0x00000000 Bit [31:5] 4 Access: Read only Value [3:0] 0000 0001 1111 Description Reserved. ADC start conversion enable bit.
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ADuC7124/ADuC7126 Data Sheet PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 25 interrupt sources on the ADuC7124/ADuC7126 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately.
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Data Sheet ADuC7124/ADuC7126 IRQEN Register Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both the IRQEN and FIQEN masks. IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an IRQ exception.
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ADuC7124/ADuC7126 Data Sheet PROGRAMMABLE PRIORITY PER INTERRUT (IRQP0/IRQP1/IRQP2/IRQP3) FIQCLR Register Name: FIQCLR Address: 0xFFFF010C IRQ_SOURCE Default Value: 0x00000000 FIQ_SOURCE Access: Write only INTERNAL ARBITER LOGIC POINTER FUNCTION (IRQVEC) INTERRUPT VECTOR FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core.
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Data Sheet ADuC7124/ADuC7126 IRQVEC Register The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register.
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ADuC7124/ADuC7126 Data Sheet Name: IRQP2 interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. Address: 0xFFFF0028 Name: IRQCONN Default Value: 0x00000000 Address: 0xFFFF0030 Access: Read/write Default Value: 0x00000000 Access: Read/write IRQP2 Register Table 132. IRQP2 MMR Bit Descriptions Bit 31 [30:28] 27 [26:24] 23 [22:20] Name Description Reserved. A priority level of 0 to 7 can be set for IRQ3. Reserved.
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Data Sheet ADuC7124/ADuC7126 FIQVEC Register The FIQ interrupt vector register, FIQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should be read only when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register.
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ADuC7124/ADuC7126 Bit [7:6] [5:4] [3:2] [1:0] Value 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 Data Sheet Name IRQ2SRC[1:0] PLA0SRC[1:0] IRQ1SRC[1:0] IRQ0SRC[1:0] Description External IRQ2 triggers on falling edge. External IRQ2 triggers on rising edge. External IRQ2 triggers on low level. External IRQ2 triggers on high level. PLA IRQ0 triggers on falling edge. PLA IRQ0 triggers on rising edge. PLA IRQ0 triggers on low level. PLA IRQ0 triggers on high level.
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Data Sheet ADuC7124/ADuC7126 In normal mode, an IRQ is generated each time the value of the counter reaches zero when counting down. It is also generated each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TxCLRI). TIMERS The ADuC7124/ADuC7126 have four general-purpose timers/counters.
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ADuC7124/ADuC7126 Data Sheet Timer0 (RTOS Timer) T0VAL Register Timer0 is a general-purpose, 16-bit timer (count down) with a programmable prescaler. The prescaler source is the core clock frequency (HCLK) and can be scaled by a factor of 1, 16, or 256. Name: T0VAL Address: 0xFFFF0304 Timer0 can be used to start ADC conversions, as shown in the block diagram in Figure 53.
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Data Sheet ADuC7124/ADuC7126 32-BIT LOAD Table 141. T0CON MMR Bit Descriptions Value 6 [5:4] 00 01 10 11 [3:2] 00 01 10 11 [1:0] Description Reserved. Timer0 enable bit. Set by the user to enable Timer0. Cleared by the user to disable Timer0 by default. Timer0 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode. Default mode. Clock select bits. HCLK. UCLK. 32.768 kHz. Reserved. Prescale. Core clock/1. Default value. Core clock/16. Core clock/256.
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ADuC7124/ADuC7126 Data Sheet Table 142. T1CON MMR Bit Descriptions Bit [31:18] 17 Value [16:12] [11:9] 000 001 010 011 8 7 6 [5:4] 00 01 10 11 [3:0] 0000 0100 1000 1111 Description Reserved. Event select bit. Set by user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 25. These events are as described in Table 126. All events are offset by two, that is, Event 2 in Table 126 becomes Event 0 for the purposes of Timer0.
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Data Sheet ADuC7124/ADuC7126 Timer2 Value Register Timer2 Control Register Name: T2VAL Name: T2CON Address: 0xFFFF0344 Address: 0xFFFF0348 Default Value: 0x0000 Default Value: 0x0000 Access: Read only Access: Read/write T2VAL is a 32-bit register that holds the current value of Timer2. This 32-bit MMR configures the mode of operation for Timer2. Table 144.
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ADuC7124/ADuC7126 Data Sheet Timer3 (Watchdog Time) T3VAL Register Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a processor reset. Name: T3VAL Address: 0xFFFF0364 Default Value: 0xFFFF Access: Read only Normal Mode Timer3 in normal mode is identical to Timer0, except for the clock source and the count-up functionality.
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Data Sheet ADuC7124/ADuC7126 T3CLRI Register Name: T3CLRI The pins required for interfacing to an external memory are shown in Table 146. Address: 0xFFFF036C Table 146. External Memory Interfacing Pins Default Value: 0x00 Access: Write only T3CLRI is an 8-bit register. Writing any value to this register on successive occassions clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode.
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ADuC7124/ADuC7126 Data Sheet XMCFG Register Name: XMCFG XMxPAR are registers that define the protocol used for accessing the external memory for each memory region. Address: 0xFFFFF000 Table 151. XMxPAR MMR Bit Descriptions Default Value: 0x00 Bit 15 Access: Read/write Description Enable byte write strobe. This bit is only used for two 8-bit memory blocks sharing the same memory region. Set by the user to gate the A0 output with the WS output.
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Data Sheet ADuC7124/ADuC7126 MCLK AD[15:0] ADDRESS DATA MSx 09123-040 AE RS Figure 58. External Memory Read Cycle MCLK AD[15:0] ADDRESS DATA EXTRA ADDRESS HOLD TIME XMxPAR (BIT 10) MSx AE BUS TURN OUT CYCLE (BIT 9) BUS TURN OUT CYCLE (BIT 9) Figure 59. External Memory Read Cycle with Address Hold and Bus Turn Cycles Rev.
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ADuC7124/ADuC7126 Data Sheet MCLK AD[15:0] ADDRESS DATA EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) 09123-042 WS Figure 60. External Memory Write Cycle with Address and Write Hold Cycles MCLK AD[15:0] ADDRESS DATA MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) 1 WRITE STROBE WAIT STATE (BIT 7 TO BIT 4) Figure 61. External Memory Write Cycle with Wait States Rev.
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Data Sheet ADuC7124/ADuC7126 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7124/ADuC7126 operational power supply voltage range is 2.7 V to 3.6 V. Separate analog and digital power supply pins (AVDD and IOVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system IOVDD line. In this mode, the part can also operate with split supplies; that is, it can use different voltage levels for each supply.
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ADuC7124/ADuC7126 Data Sheet GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the ADuC7124/ADuC7126-based designs to achieve optimum performance from the ADCs and DAC. Although the part has separate pins for analog and digital ground (AGND and IOGND), the user must not tie these to two separate ground planes unless the two ground planes are connected very close to the part.
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Data Sheet ADuC7124/ADuC7126 3.3V POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7124/ADuC7126. For LVDD below 2.40 V typical, the internal POR holds the part in reset. As LVDD rises above 2.41 V, an internal timer times out for typically 128 ms before the part is released from reset. The user must ensure that the power supply, IOVDD, reaches a stable 2.7 V minimum level by this time.
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ADuC7124/ADuC7126 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 48 1 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 17 0.25 MIN 7.50 REF 0.30 0.23 0.18 0.20 REF 04-04-2012-A FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE 16 BOTTOM VIEW 0.80 MAX 0.65 TYP 12° MAX 4.70 SQ 4.
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Data Sheet ADuC7124/ADuC7126 ORDERING GUIDE Model 1 ADuC7124BCPZ126 ADC Channels 10 DAC Channels 2 Flash/RAM 126 kB/32 kB GPIO 30 Downloader UART Temperature Range −40°C to +125°C ADuC7124BCPZ126-RL 10 2 126 kB/32 kB 30 UART −40°C to +125°C ADuC7126BSTZ126 ADuC7126BSTZ126-RL ADuC7126BSTZ126I ADuC7126BSTZ126IRL EVAL-ADuC7124QSPZ 12 12 12 12 4 4 4 4 126 kB/32 kB 126 kB/32 kB 126 kB/32 kB 126 kB/32 kB 40 40 40 40 UART UART I2C I2C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +
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ADuC7124/ADuC7126 Data Sheet NOTES Rev.
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Data Sheet ADuC7124/ADuC7126 NOTES Rev.
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ADuC7124/ADuC7126 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09123-0-5/12(C) Rev.