Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 10 of 108
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DOSU
Data output setup before SCLK edge 75 ns
t
DSU
Data input setup time before SCLK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SR
SCLK rise time 5 12.5 ns
t
SF
SCLK fall time 5 12.5 ns
1
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
09123-031
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)